20098 Commits

Author SHA1 Message Date
Arthur Eubanks
323451ab88
[X86] Set SHF_X86_64_LARGE for globals with explicit well-known large section name (#74381)
Globals marked with the .lbss/.ldata/.lrodata should automatically be
treated as large.
Do this regardless of the code model for consistency when mixing object
files compiled with different code models.

Basically the other half of #70748.

Example in the wild:
https://codebrowser.dev/qt5/qtbase/src/testlib/qtestcase.cpp.html#1664
2023-12-05 08:26:08 -08:00
Nikita Popov
eecb99c5f6 [Tests] Add disjoint flag to some tests (NFC)
These tests rely on SCEV looking recognizing an "or" with no common
bits as an "add". Add the disjoint flag to relevant or instructions
in preparation for switching SCEV to use the flag instead of the
ValueTracking query. The IR with disjoint flag matches what
InstCombine would produce.
2023-12-05 14:09:36 +01:00
Simon Pilgrim
dd04e18304 [X86]fold-pcmpeqd-2.ll - replace X32 check prefix with X86
We use X32 for gnux32 triples - X86 should be used for 32-bit triples
2023-12-05 12:34:55 +00:00
Philip Reames
943f3e52a0 [X86] Remove x86-experimental-unordered-atomic-isel option and associated code
This option enables an experimental lowering for unordered atomics I worked
on a few years back.  It never reached production quality, and hasn't been
worked on in years.  So let's rip it out.

This wasn't a crazy idea, but I hit some stumbling block which prevented me
from pushing it across the finish line.  From the look of 027aa27, that
change description is probably a good summary.  I don't remember the
details any longer.
2023-12-04 20:03:38 -08:00
Vitaly Buka
7e3aeee3bf
[NFC][asan] Replace AsanInited/ENSURE_ASAN_INITED with TryAsanInitFromRtl (#74172) 2023-12-04 14:56:21 -08:00
Seth Brenith
f6c7baea09
[Win/x64] Update preserve_most to treat XMM registers like C (#73866)
As [scottmcm
described](https://discourse.llvm.org/t/conv-c-and-conv-preservemost-mix-badly-on-windows-x64/73054),
the `preserve_most` calling convention, as currently implemented, is a
bad fit for Windows on x64. The intent of `preserve_most` is "to make
the code in the caller as unintrusive as possible", but `preserve_most`
causes the caller to spill and restore ten SIMD registers. It would be
preferable to make `preserve_most` treat the XMM registers however the C
calling convention does on the target operating system.

This is a breaking change, but the documentation indicates that
`preserve_most` is still experimental, so I believe that ABI
compatibility is not yet a requirement.
2023-12-04 11:53:36 -08:00
Craig Topper
5bc391a7c9
[SelectionDAG] Use getVectorElementPointer in DAGCombiner::replaceStoreOfInsertLoad. (#74249)
This ensures we clip the index to be in bounds of the vector we are
inserting into. If the index is out of bounds the results of the insert
element is poison. If we don't clip the index we can write memory that
was not part of the original store.

Fixes #74248.
2023-12-04 11:11:37 -08:00
Simon Pilgrim
c4b795df80 [X86] Regenerate combine-or.ll 2023-12-04 15:20:02 +00:00
Simon Pilgrim
99fd62adff [X86] Add tests for constant nontemporal vector stores
Extends the zero-vector test coverage in nontemporal-3.ll
2023-12-04 11:11:34 +00:00
Shengchen Kan
68d6fe508c
[X86][CodeGen] Prefer KMOVkk_EVEX than KMOVkk when EGPR is supported (#74048)
In memory fold table, we have

```
 {X86::KMOVDkk, X86::KMOVDkm, 0},
 {X86::KMOVDkk_EVEX, X86::KMOVDkm_EVEX, 0}
```

where `KMOVDkm_EVEX` can use EGPR as base and index registers, while
`KMOVDkm` can't. Hence, though `KMOVkk` does not have any GPR operands,
we prefer to use `KMOVDkk_EVEX` to help register allocation.

It will be compressed to `KMOVDkk` in EVEX2VEX pass if memory folding
does not happen.
2023-12-02 22:43:02 +08:00
Arthur Eubanks
d8a04398f9 Reland [X86] With large code model, put functions into .ltext with large section flag (#73037)
So that when mixing small and large text, large text stays out of the
way of the rest of the binary.

This is useful for mixing precompiled small code model object files and
built-from-source large code model binaries so that the the text
sections don't get merged.

The reland fixes an issue where a function in the large code model would reference small data without GOTOFF.

This was incorrectly reverted in 76f78ecc789d58baa3a88b2fe2a57428f07e5362.
2023-12-01 14:23:44 -08:00
Dmitri Gribenko
76f78ecc78 Revert "Reland [X86] With large code model, put functions into .ltext with large section flag (#73037)"
This reverts commit 4bf8a688956a759b7b6b8d94f42d25c13c7af130.

This commit seems to be breaking the semantics of the
ObjectFile::isSectionText method, which breaks numba/llvmlite bindings.
2023-12-01 17:18:14 +01:00
Paul Kirth
cfe1ece833
[clang][llvm][fatlto] Avoid cloning modules in FatLTO (#72180)
https://github.com/llvm/llvm-project/issues/70703 pointed out that
cloning LLVM modules could lead to miscompiles when using FatLTO.

This is due to an existing issue when cloning modules with labels (see
#55991 and #47769). Since this can lead to miscompilation, we can avoid
cloning the LLVM modules, which was desirable anyway.

This patch modifies the EmbedBitcodePass to no longer clone the module
or run an input pipeline over it. Further, it make FatLTO always perform
UnifiedLTO, so we can still defer the Thin/Full LTO decision to
link-time. Lastly, it removes dead/obsolete code related to now defunct
options that do not work with the EmbedBitcodePass implementation any
longer.
2023-11-30 17:09:34 -08:00
Arthur Eubanks
4bf8a68895 Reland [X86] With large code model, put functions into .ltext with large section flag (#73037)
So that when mixing small and large text, large text stays out of the
way of the rest of the binary.

This is useful for mixing precompiled small code model object files and
built-from-source large code model binaries so that the the text
sections don't get merged.

The reland fixes an issue where a function in the large code model would reference small data without GOTOFF.
2023-11-30 15:17:17 -08:00
Douglas Yung
c12de14876 Revert "[X86] Canonicalize fp zero vectors from bitcasted integer zero vectors"
This reverts commit 169db80e41936811c6744f2c513a1ed00d97f10e.

This change is causing many test failures on Windows bots:
- https://lab.llvm.org/buildbot/#/builders/235/builds/3616
- https://lab.llvm.org/buildbot/#/builders/233/builds/4883
- https://lab.llvm.org/buildbot/#/builders/216/builds/31174
2023-11-30 11:59:50 -08:00
Simon Pilgrim
169db80e41 [X86] Canonicalize fp zero vectors from bitcasted integer zero vectors
Generic code is supposed to handle this but can be blocked by hasOneUse checks.

Noticed while investigating #26392
2023-11-30 18:33:52 +00:00
Simon Pilgrim
539e60c34a [X86] X86FixupVectorConstantsPass - consistently use non-DQI 128/256-bit subvector broadcasts
Without the predicate there's no benefit to using the DQI variants instead of the default AVX512F instructions
2023-11-30 18:33:52 +00:00
Shengchen Kan
a4e1aa256b
[X86][tablgen] Auto-gen broadcast tables (#73654)
1. Add TB_BCAST_SH for FP16
2. Auto-gen 4 broadcast tables BroadcastTable[1-4]

issue: https://github.com/llvm/llvm-project/issues/66360
2023-11-30 22:24:31 +08:00
Simon Pilgrim
1d20b009a0 [X86] Enable v8f16/v16f16/v32f16 FCOPYSIGN custom lowering on SSE2/AVX/AVX512 targets 2023-11-30 11:48:33 +00:00
Simon Pilgrim
e653e0303d [X86] Add fcopysign vector test coverage 2023-11-30 11:33:39 +00:00
Simon Pilgrim
d2856ff457 [X86] Enable v32f16 FNEG custom lowering on AVX512 targets 2023-11-30 10:07:01 +00:00
Simon Pilgrim
8851e411ed [X86] Enable v16f16 FNEG custom lowering on AVX targets 2023-11-30 10:07:01 +00:00
Simon Pilgrim
06b9d92e0e [X86] Enable v8f16 FABS custom lowering on SSE2 targets 2023-11-30 10:07:00 +00:00
Simon Pilgrim
abc60e9808 [X86] vec_fabs.ll - add SSE test coverage 2023-11-30 10:07:00 +00:00
Simon Pilgrim
9d4c3e9035 [X86] Enable v8f16 FNEG custom lowering 2023-11-30 10:07:00 +00:00
Shengchen Kan
eb64697a7b [X86][Codegen] Correct the domain of VP2INTERSECT
GenericDomain -> SSEPackedInt

Found by #73654
2023-11-30 17:56:21 +08:00
Shengchen Kan
511ba45a47
[X86][MC][CodeGen] Support EGPR for KMOV (#73781)
KMOV is essential for copy between k-registers and GPRs.
R16-R31 was added into GPRs in #70958, so we extend KMOV for these new
registers first.

This patch
1.  Promotes KMOV instructions from VEX space to EVEX space
2.  Emits prefix {evex} for the EVEX variants
3. Prefers EVEX variant than VEX variant in ISEL and optimizations for
better RA

EVEX variants will be compressed to VEX variants by existing EVEX2VEX
pass if no EGPR is used.

RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
TAG: llvm-test-suite && CPU2017 can be built with feature egpr
successfully.
2023-11-30 16:13:51 +08:00
David Li
f688e09012
Enable custom lowering of fabs_v16f16 with AVX and fabs_v32f16 with A… (#73565)
This is the last patch for fabs lowering. v32f16 works for AVX as well
with the patch (with type legalization).
2023-11-29 09:39:53 -08:00
Simon Pilgrim
244389ad17 [X86] Add fneg vector test coverage 2023-11-29 15:03:26 +00:00
Simon Pilgrim
53f3e59e59 [X86] Rename vec_fneg.ll to combine-fneg.ll
These tests are for fneg canonicalization combines, not codegen coverage tests like most of the other vec_* test files.
2023-11-29 15:03:25 +00:00
Simon Pilgrim
0fac9da734 [DAG] getNode() - relax (zext (trunc x)) -> x fold iff the upper bits are known zero.
Just leave the (zext (trunc (and x, c))) pattern which is still being used to create some zext_inreg patterns.
2023-11-29 10:38:11 +00:00
Simon Pilgrim
621183cb45 [X86] Add test case showing failure to remove unnecessary zext from address math
Thanks to @yubingex007-a11y for the original test case
2023-11-29 10:38:11 +00:00
Qiu Chaofan
403ab9ac74 [NFC] Update X86 frem CodeGen case 2023-11-29 16:53:34 +08:00
Arthur Eubanks
d8d9394cb0 Revert "[X86] With large code model, put functions into .ltext with large section flag (#73037)"
This reverts commit 38e435895779c6f0e6c47a171f3b300ad99828b3.

May be culprit for https://lab.llvm.org/buildbot/#/builders/37/builds/28079/steps/9/logs/stdio.
2023-11-28 14:14:40 -08:00
Arthur Eubanks
38e4358957
[X86] With large code model, put functions into .ltext with large section flag (#73037)
So that when mixing small and large text, large text stays out of the
way of the rest of the binary.

This is useful for mixing precompiled small code model object files and
built-from-source large code model binaries so that the the text
sections don't get merged.
2023-11-28 12:55:17 -08:00
Simon Pilgrim
eba50929b8 [X86] X86DAGToDAGISel - fix typo in #73126
We were casting the LoadSDNode from the wrong node in the base pointer uses list, meaning the ptr/chain comparison were comparing against themselves.
2023-11-28 10:17:57 +00:00
paperchalice
61e58c4dc1
[CodeGen] Port DwarfEHPrepare to new pass manager (#72500)
Co-authored-by: PaperChalice <example@example.com>
2023-11-28 17:53:25 +09:00
Shengchen Kan
a3b7b2d635
[X86][CodeGen] Not compress EVEX into VEX when R16-R31 is used (#73604)
b/c VEX prefix can not encode R16-R31.
2023-11-28 11:40:48 +08:00
Shengchen Kan
d9221da72b
[X86][MC] Keep backward compatibility in inline asm for constraints (#73529)
Not use r16-r31 with 'q','r','l' constraint for backward compatibility
2023-11-28 09:42:03 +08:00
David Li
c2ba2b2190
Fix ISel crash when lowering BUILD_VECTOR (#73186)
512bit vpbroadcastw is available only with AVX512BW. Avoid lowering
BUILD_VEC into vbroard_cast node when the condition is not met. This
fixed a crash (see the added new test).
2023-11-27 11:09:46 -08:00
Bjorn Pettersson
30afb21547 Revert "[MCP] Enhance MCP copy Instruction removal for special case (#70778)"
This reverts commit cae46f6210293ba4d3568eb21b935d438934290d.

Reverted due to miscompiles.
See https://github.com/llvm/llvm-project/issues/73512
2023-11-27 19:39:40 +01:00
Simon Pilgrim
286905351f [X86] vector-interleaved tests - add AVX512F/AVX512DQ/AVX512BW/AVX512DQBW-ONLY common prefixes to merge more SLOW/FAST checks
Not used by many vector-interleaved tests, but its a LOT easier to maintain if we use the same prefixes for all of them.
2023-11-27 15:06:24 +00:00
Simon Pilgrim
edf645616f [X86] Regenerate vector-interleaved-store-i64-stride-4.ll 2023-11-27 13:48:36 +00:00
Shengchen Kan
cb112eb16c
[X86][CodeGen] Teach frame lowering to spill/reload registers w/ PUSHP/POPP, PUSH2[P]/POP2[P] (#73292)
#73092 supported the encoding/decoding for PUSHP/POPP
#73233 supported the encoding/decoding for PUSH2[P]/POP2[P]

In this patch, we teach frame lowering to spill/reload registers w/
these instructions.

1. Use PPX for balanced spill/reload
2. Use PUSH2/POP2 for continuous spills/reloads
3. PUSH2/POP2 must be 16B-aligned on the stack, so pad when necessary
2023-11-27 21:37:07 +08:00
Simon Pilgrim
11276563c8 [X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of the same ptr (#73126)
If we are loading the same ptr at different vector widths, then reuse the largest load and just extract the low subvector.

Unlike the equivalent VBROADCAST_LOAD/SUBV_BROADCAST_LOAD folds which can occur in DAG, we have to wait until DAGISel otherwise we can hit infinite loops if constant folding recreates the original constant value.

This is mainly useful for better constant sharing.
2023-11-27 10:26:26 +00:00
Shengchen Kan
27c0bc9cae
[X86][MC] Allow to specify any of the 8/16/32/64 register names interchangeably for R16-R31 (#73421) 2023-11-27 15:25:19 +08:00
Phoebe Wang
ea81e31aa1
[X86][AVX10] Allow AVX10 use VBMI2 instructions (#73276) 2023-11-24 12:54:30 +08:00
Björn Pettersson
3114bd32e7
[StackColoring] Do not drop AA metadata when not doing remappings (#71958)
In the StackColoring pass we first scan for possible stack slot merges.
A SlotRemap map is setup with the remappings that should be performed.
Then the main work is done by calling remapInstructions and providing
that map.

Most of the work in remapInstructions would just be a waste of time in
situations when the SlotRemap map is empty, but it turns out that the
part that adjusts Alias Analysis information could end up dropping AA
metadata even when there are no stack slot merges being done. This
happens since all instruction's machine memory operands are considered,
and if we can't determine the underlying object that is accessed (using
getUnderlyingObjectsForCodeGen) then we conservatively drop AA metadata.

This patch simply avoids calling remapInstructions if we don't intend to
do any remappings (i.e. if SlotRemap is empty). That avoids touching AA
metadata when all we do is to remove lifetime markers. That seems like a
safe thing to do, as it is the same thing as happens when we bail out
early due to other reasons (e.g. when only having one lifetime marker).

For targets that do not care about Alias Analysis information after the
StackColoring pass this shouldn't have any impact, except that it might
improve compile time slightly as we now skip spending time in
remapInstructions when not doing any stack merges.
2023-11-23 18:10:40 +01:00
Simon Pilgrim
381efa4960 Revert rG67275263b3b781a "[X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of the same ptr (#73126)"
Missed an issue that we were calling continue from within the for loop - fixed version incoming shortly.
2023-11-23 16:50:58 +00:00
Simon Pilgrim
67275263b3
[X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of the same ptr (#73126)
If we are loading the same ptr at different vector widths, then reuse the larger load and just extract the low subvector.

Unlike the equivalent VBROADCAST_LOAD/SUBV_BROADCAST_LOAD folds which can occur in DAG, we have to wait until DAGISel otherwise we can hit infinite loops if constant folding recreates the original constant value.

This is mainly useful for better constant sharing.
2023-11-23 14:10:23 +00:00