3 Commits

Author	SHA1	Message	Date
Roman Lebedev	80e8f2beeb	[NFC] Port all (but one) LICM tests to -passes= syntax	2022-12-07 20:53:15 +03:00
Mingming Liu	8aa800614b	[AArch64][CostModel] Detects that {extract,insert}-element at lane 0 has the same cost as the other lane for vector instructions in the IR. ... Currently, {extract,insert}-element has zero cost at lane 0 [1]. However, there is a cost (by fmov instruction [2], or ext/ins instruction) to move values from SIMD registers to GPR registers, when the element is used explicitly as integers. See https://godbolt.org/z/faPE1nTn8, when fmov is generated for d* register -> x* register conversion. Implementation-wise, add a private method `AArch64TTIImpl::getVectorInstrCostHelper` as a helper function. This way, instruction-based method could share the core logic (e.g., returning zero cost if type is legalized to scalar). [1] 2cf320d41e/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp (L1853) [2] 2cf320d41e/llvm/lib/Target/AArch64/AArch64InstrInfo.td (L8150-L8157) Differential Revision: https://reviews.llvm.org/D128302	2022-09-09 09:47:30 -07:00
Mingming Liu	b242e8502c	[AArch64][NFC] Prepare test cases (for D128302) to show more accurate cost estimation of extract-element could generate better assembly code. ... Pre-commit the test cases (for D128302) to show that more accurate cost estimation of extract-element could generate better code. Differential Revision: https://reviews.llvm.org/D128945	2022-07-07 09:39:29 -07:00