Move vector pointer generation to a separate VPVectorPointerRecipe. This untangles address computation from the memory recipes future and is also needed to enable explicit unrolling in VPlan. https://github.com/llvm/llvm-project/pull/72164
Those CPUs can benefit from additional interleaving. Reviewed By: jroelofs Differential Revision: https://reviews.llvm.org/D141499
Add extra tests for interleaving heuristics for different AArch64 CPUs.
