14 Commits

Author SHA1 Message Date
Matthias Springer
32c3decb77
[mlir][vector] Modernize vector.transpose op (#72594)
* Declare arguments/results with `let` statements.
* Rename `transp` to `permutation`.
* Change type of `transp` from `I64ArrayAttr` to `DenseI64ArrayAttr`
(provides direct access to `ArrayRef<int64_t>` instead of `ArrayAttr`).
2023-11-20 11:25:35 +01:00
Diego Caballero
98f6289a34 [mlir][Vector] Add support for Value indices to vector.extract/insert
`vector.extract/insert` ops only support constant indices. This PR is
extending them so that arbitrary values can be used instead.

This work is part of the RFC: https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops

Differential Revision: https://reviews.llvm.org/D155034
2023-09-22 00:39:32 +00:00
Mikhail Goncharov
0a0aff2d24 fix unused variable warnings in conditionals
warning was updated in 92023b15099012a657da07ebf49dd7d94a260f84
2023-08-30 19:09:27 +02:00
Jakub Kuderski
4a3899577a [mlir][arith] Validate pass options in arith-int-narrowing
Exist gracefully instead of triggering an assertions.

Fixes: https://github.com/llvm/llvm-project/issues/64257

Reviewed By: springerm

Differential Revision: https://reviews.llvm.org/D156694
2023-07-31 11:32:01 -04:00
Jakub Kuderski
fc19204918 [mlir][arith] Add narrowing patterns for index casts
These rely on the `ValueBounds` interace and its utility function to
compute constant bounds. This allows us to optimize `linalg.index`
values cast to integer types.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149538
2023-05-03 13:55:02 -04:00
Jakub Kuderski
9701c5abd6 [mlir][arith] Add narrowing patterns for max*i and min*i
Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149583
2023-05-02 10:50:07 -04:00
Jakub Kuderski
46740dd02b [mlir][arith] Add narrowing patterns for subi, divsi, and divui
Each of these ops is compatible with only one extension kind and
produces an extra result bit.

I checked these transformation in Alive2:
1. subi + extsi: https://alive2.llvm.org/ce/z/ipmZZA
2. divsi + extsi: https://alive2.llvm.org/ce/z/fAcqUv
3. divui + extui: https://alive2.llvm.org/ce/z/QZJpFp

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149531
2023-05-02 10:44:29 -04:00
Jakub Kuderski
e2f7563d7c [mlir][arith] Add narrowing patterns for addi and muli
These two ops are handled in a very similar way -- the only difference
in the number result bits produced.

I checked these transformation with Alive2:
1.  addi + sext: https://alive2.llvm.org/ce/z/3NSs9T
2.  addi + zext: https://alive2.llvm.org/ce/z/t7XHOT
3.  muli + sext: https://alive2.llvm.org/ce/z/-7sfW9
4.  muli + zext: https://alive2.llvm.org/ce/z/h4yntF

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149530
2023-05-02 10:10:10 -04:00
Jakub Kuderski
7f3b0e5845 [mlir][arith] Add narrowing patterns to commute more vector ops
This commutes the extension (`arith.extsi`, `arith.extui`) over the
following vector ops: `vector.broadcast`, `vector.shape_cast`,
`vector.transpose`, `vector.flat_transpose`.

I focused on these as I saw them getting created by vector unroll
patterns. Maybe except `vector.flat_transpose`.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149534
2023-05-01 14:32:57 -04:00
Jakub Kuderski
3ff870881f [mlir][arith] Add narrowing patterns for other insertion ops
Allow to commute extension ops over `vector.insertelement` and
`vector.insert_strided_slice`.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149509
2023-05-01 14:29:02 -04:00
Jakub Kuderski
49df068836 [mlir][arith][NFC] Simplify narrowing patterns with a wrapper type
Add a new wraper type that represents either of `ExtSIOp` or `ExtUIOp`.
This is to simplify the code by using a single type, so that we do not
have to use templates or branching to handle both extension kinds.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149485
2023-05-01 13:31:31 -04:00
Jakub Kuderski
33017e5a3f [mlir][arith] Add narrowing pattern to commute extension over insertion
This enabled more optimization opportunities by moving
zero/sign-extension closer to the use.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149282
2023-04-28 16:17:44 -04:00
Jakub Kuderski
09043a26c8 [mlir][arith] Add patterns to commute extension over vector extraction
This moves zero/sign-extension ops closer to their use and exposes more
narrowing optimization opportunities.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149233
2023-04-28 13:48:50 -04:00
Jakub Kuderski
da0730b908 [mlir][arith] Add initial integer bitwidth narrowing pass
This pass reduces the logical complexity of arith ops by choosing
narrowest supported operand bitwidth. On some targets like mobile GPUs,
narrower bitwidths also bring better runtime performance.

The first batch of rewrites handles a simple case of `arith.sitofp`
and `arith.uitofp` with zero/sign-extended inputs. In future revisions,
I plan to extend it with the following:
-  Propagating sign/zero-extensions through bit-pattern-preserving ops,
   e.g., vector transpose, broadcast, insertions/extractions.
-  Handling `linalg.index` using the `ValueBounds` interface.
-  Handling more arith ops.

Reviewed By: springerm, antiagainst

Differential Revision: https://reviews.llvm.org/D149118
2023-04-25 22:33:11 -04:00