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Author	SHA1	Message	Date
Mehdi Amini	f6fb639c76	Fix memoery leak in MLIR use-def list ordering test	2023-05-21 20:11:30 -07:00
Mehdi Amini	f58d2cc5a0	Fix MLIR build on powerpc The RNG initalization relied on implicit conversion that wasn't guaranteed in the MLIR TestUseListOrders. Also made the RNG state a pass member, the random sequence is not not reset for each op anymore.	2023-05-21 18:04:39 -07:00
Matteo Franciolini	612781918f	Preserve use-list orders in mlir bytecode This patch implements a mechanism to read/write use-list orders from/to the mlir bytecode format. When producing bytecode, use-list orders are appended to each value of the IR. When reading bytecode, use-lists orders are loaded in memory and used at the end of parsing to sort the existing use-list chains. Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D149755	2023-05-21 16:48:12 -07:00

Author

SHA1

Message

Date

Mehdi Amini

f6fb639c76

Fix memoery leak in MLIR use-def list ordering test

2023-05-21 20:11:30 -07:00

Mehdi Amini

f58d2cc5a0

Fix MLIR build on powerpc

The RNG initalization relied on implicit conversion that wasn't guaranteed in
the MLIR TestUseListOrders.
Also made the RNG state a pass member, the random sequence is not not reset
for each op anymore.

2023-05-21 18:04:39 -07:00

Matteo Franciolini

612781918f

Preserve use-list orders in mlir bytecode

This patch implements a mechanism to read/write use-list orders from/to the mlir bytecode format. When producing bytecode, use-list orders are appended to each value of the IR. When reading bytecode, use-lists orders are loaded in memory and used at the end of parsing to sort the existing use-list chains.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D149755

2023-05-21 16:48:12 -07:00

3 Commits