367 Commits

Author SHA1 Message Date
Matt Arsenault
decbd29f9e
Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (#74056)
This reverts commit ef388334ee5a3584255b9ef5b3fefdb244fa3fd7.

The referenced issue violates the spec for finite-only math only by
using a return value for a constant infinity. If the interpretation
is results and arguments cannot violate nofpclass, then any
std::numeric_limits<T>::infinity() result is invalid under
-ffinite-math-only. Without this interpretation the utility of
nofpclass is slashed.
2024-02-08 14:12:39 +05:30
Yingwei Zheng
cb8d83a77c
[InstCombine] Fix assertion failure in issue80597 (#80614)
The assertion in #80597 failed when we were trying to compute known bits
of a value in an unreachable BB.

859b09da08/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (L749-L810)

In this case, `SignBits` is 30 (deduced from instr info), but `Known` is
`10000101010111010011110101000?0?00000000000000000000000000000000`
(deduced from dom cond). Setting high bits of `lshr Known, 1` will lead
to conflict.

This patch masks out high bits of `Known.Zero` to address this problem.

Fixes #80597.
2024-02-06 01:29:38 +08:00
Nikita Popov
f412b78ffc [InstCombine] Return poison if all lanes are poison 2023-12-19 12:43:23 +01:00
Nikita Popov
9d4557920f [InstCombine] Don't treat undef as poison in demanded element simplification
We can only set PoisonElts if the element is poison, not if it is
undef.
2023-12-19 12:26:48 +01:00
Nikita Popov
e400c59beb Revert "[InstCombine] Favour m_Poison in SimplifyDemandedVectorElts"
This reverts commit 318d5bff0b65aa7d52fc7004d49587416f0fb564.

Has incomplete test updates.
2023-12-18 18:08:57 +01:00
Antonio Frighetto
318d5bff0b [InstCombine] Favour m_Poison in SimplifyDemandedVectorElts
A miscompilation issue has been addressed with refined checking.
2023-12-18 17:28:39 +01:00
Nikita Popov
a5f3415533 [InstCombine] Replace non-demanded undef vector with poison
If an operand (esp to shufflevector or insertelement) is not
demanded, canonicalize it from undef to poison.
2023-12-18 16:12:37 +01:00
Nikita Popov
d0605e21af [InstCombine] Canonicalize splat shuffles to use poison operand
If the splat shuffle is represented using an undef RHS, replace it
with poison.
2023-12-18 15:57:49 +01:00
Nikita Popov
465ecf872e [InstCombine] Rename UndefElts -> PoisonElts (NFC)
In line with updated shufflevector semantics, this represents the
poison elements rather than undef elements now. This commit is a
pure rename, without any logic changes.
2023-12-18 12:36:19 +01:00
Antonio Frighetto
151ddf07a6 [InstCombine] Stop propagating undef when element is demanded
Do not poison `undef` demanded elements in `SimplifyDemandedVectorElts`.
A miscompilation issue has been addressed with refined checking.

Proofs: https://alive2.llvm.org/ce/z/WA5oD5.
2023-12-17 21:41:03 +01:00
Nikita Popov
9100228e45 [InstCombine] Fix insertion point 2023-12-14 15:27:17 +01:00
Fujun Han
7be5dabbc2
[InstCombine] Change (add x, c) to (xor x, c) (#75129)
Change (add x, c) to (xor x, c) iff c is constant and c equals the top bit of the demanded bits.
Alive2: https://alive2.llvm.org/ce/z/DKmkwF

---------

Signed-off-by: Peter Han <fujun.han@iluvatar.com>
Co-authored-by: Peter Han <fujun.han@iluvatar.com>
2023-12-14 21:19:15 +08:00
Craig Topper
56248caa3b
[InstCombine] Explicitly set disjoint flag when converting xor to or. (#74229) 2023-12-06 09:41:59 -08:00
Craig Topper
76cd0355cb [InstCombine] Preserve exact instruction name for xor->or transform in SimplifyDemandedUseBits.
We were previously retaining the name with a numeric suffix.
2023-12-02 23:21:59 -08:00
Craig Topper
bdcf2087d9 Recommit "[InstCombine] Retain exact instruction name for some cases in SimplifyDemandedUseBits."
It looks like my original patch got caught up in
ef388334ee5a3584255b9ef5b3fefdb244fa3fd7 that was reverting a different
patch.

Original message:
Retain name for SExt->ZExt and AShr->LShr. Previously SExt->ZExt copied
the name with a numeric suffix. AShr->LShr dropped it.
2023-12-02 20:53:34 -08:00
Craig Topper
7ec4f6094e
[InstCombine] Infer disjoint flag on Or instructions. (#72912)
The disjoint flag was recently added to IR in #72583

We already set it when we turn an add into an or. This patch sets it on Ors that weren't converted from an Add.
2023-12-02 14:11:12 -08:00
Nikita Popov
10b44fb6a3 [InstCombine] Add KnownBits consistency assertion behind option (NFC)
I'm occasionally using this to find cases where computeKnownBits()
and SimplifyDemandedBits() went out of sync.

This option is not enabled by default (even under EXPENSIVE_CHECKS)
because it has a number of known failures in our tests. The reason
for this failures is that computeKnownBits() performs recursive
queries using the original context instruction, while
SimplifyDemandedBits() uses the current instruction. This is
something we can improve, but using the original context wouldn't
always be safe in this context (when non-speculatable instructions
are involved).
2023-11-30 14:52:47 +01:00
Nikita Popov
2031e7226c [InstCombine] Require non-demanded known bits to be accurate (NFC)
In practice this is already true, and having this as an explicit
guarantee is useful for #72912. I don't think there is any good
reason why we would want to produce incorrect KnownBits results
for non-demanded bits.
2023-11-30 14:26:57 +01:00
Nikita Popov
062058ef36 [InstCombine] Use analyzeKnownBitsFromAndXorOr() in multi-use demanded bits
We were using this helper in single-use demanded bits but not
multi-use demanded bits.

This fixes an assertion failure when asserting consistency between
computeKnownBits() and SimplifyDemandedBits().
2023-11-30 14:22:48 +01:00
Nikita Popov
1566380e6b [ValueTracking] Switch analyzeKnownBitsFromAndXorOr() to use SimplifyQuery (NFC)
It already used it internally, make the public API use it as well.
2023-11-30 14:06:05 +01:00
Nikita Popov
b8a5a015d1 [InstCombine] Use pointer alignment in SimplifyDemandedBits
For parity with computeKnownBits(). This came up when adding a
consistency assertion.
2023-11-30 13:56:42 +01:00
Nikita Popov
1116e4f5dc [ValueTracking] Rename computeKnownBitsFrom{Assume -> Context} (NFC)
In preparation for handling non-assume context-sensitive facts.
2023-11-28 14:57:24 +01:00
Craig Topper
d9962c400f
[IR] Add disjoint flag for Or instructions. (#72583)
This flag indicates that every bit is known to be zero in at least one
of the inputs. This allows the Or to be treated as an Add since there is
no possibility of a carry from any bit.

If the flag is present and this property does not hold, the result is
poison.

This makes it easier to reverse the InstCombine transform that turns Add
into Or.

This is inspired by a comment here
https://github.com/llvm/llvm-project/pull/71955#discussion_r1391614578

Discourse thread
https://discourse.llvm.org/t/rfc-add-or-disjoint-flag/75036
2023-11-24 08:49:19 -08:00
Nikita Popov
eb5199e8d4 [InstCombine] Avoid some uses of ConstantExpr::getLShr() (NFC)
Use the constant folding API instead. As we're working on
ImmConstant, it is guaranteed to succeed.
2023-11-10 15:46:14 +01:00
Nikita Popov
c2a1966627 [InstCombine] Remove bitcast handling from SimplifyDemandedBits
The complex set of type checks in this code reduces down to
"always return nullptr". Drop the code to use the default
implementation instead, which will just compute the KnownBits
for the bitcast.
2023-11-10 15:25:39 +01:00
Philip Reames
23099ac239
Add known and demanded bits support for zext nneg (#70858)
zext nneg was recently added to the IR in #67982.   This patch teaches
demanded bits and known bits about the semantics of the instruction, and
adds a couple of test cases to illustrate basic functionality.
2023-11-06 18:47:56 -08:00
Philip Reames
9593cde70b
[instcombine] Drop zext nneg flag when simplify operand (#71088)
This fixes a miscompile introduced in the recent #67982, and likely
exposed in changes since to infer and leverage the same. No active bug
reports as of yet.

This was noticed in
https://github.com/llvm/llvm-project/pull/70858#discussion_r1378203532.
2023-11-02 11:43:57 -07:00
Noah Goldstein
edb9e9a5fb [InstCombine] Implement SimplifyDemandedBits for llvm.ptrmask
Logic basically copies 'and' but we can't return a constant if the
result == rhs (mask) so that case is skipped.
2023-11-01 23:50:35 -05:00
Nikita Popov
b47ff36134
[InstCombine] Drop exact flag instead of increasing demanded bits (#70311)
Demanded bit simplification for lshr/ashr will currently demand the low
bits if the exact flag is set. This is because these bits must be zero
to satisfy the flag.

However, this means that our demanded bits simplification is worse for
lshr/ashr exact than it is for plain lshr/ashr, which is generally not
desirable.

Instead, drop the exact flag if a demanded bits simplification of the
operand succeeds, which may no longer satisfy the exact flag.

This matches what we do for the exact flag on udiv, as well as the
nuw/nsw flags on add/sub/mul.
2023-10-26 13:12:30 +02:00
Nikita Popov
d4300154b6 Revert "[ValueTracking] Remove by-ref computeKnownBits() overloads (NFC)"
This reverts commit b5743d4798b250506965e07ebab806a3c2d767cc.

This causes some minor compile-time impact. Revert for now, better
to do the change more gradually.
2023-10-16 14:04:09 +02:00
Nikita Popov
b5743d4798 [ValueTracking] Remove by-ref computeKnownBits() overloads (NFC)
Remove the old overloads that accept KnownBits by reference, in
favor of those that return it by value.
2023-10-16 13:00:31 +02:00
Leonard Chan
ef388334ee Revert "Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass""
This reverts commit 5a36904c515b.

Reverted because this breaks some floating point operations. See the
comment on https://github.com/llvm/llvm-project/commit/5a36904c515b.
2023-10-12 20:23:39 +00:00
Craig Topper
98b114d1c7
[InstCombine] Retain exact instruction name for some cases in SimplifyDemandedUseBits. (#68371)
Retain name for SExt->ZExt and AShr->LShr. Previously SExt->ZExt copied
the name with a numeric suffix. AShr->LShr dropped it.
2023-10-06 09:11:36 -07:00
Matt Arsenault
091f4f496b InstCombine: Handle copysign in SimplifyDemandedFPClass
https://reviews.llvm.org/D158650
2023-10-05 09:55:27 -07:00
Matt Arsenault
5a36904c51 Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"
This reverts commit 26bb22b0c89e9b27576fd1f5683e0bc9ac3b4ec9.
2023-10-05 07:49:38 -07:00
Jonas Hahnfeld
26bb22b0c8 Revert "InstCombine: Introduce SimplifyDemandedUseFPClass"
It causes a test failure of clang/test/Headers/__clang_hip_math.hip:
https://lab.llvm.org/buildbot/#/builders/109/builds/75022

This reverts commit 59c6e2e9c1beee0bc73922fe44c9fd4462289847.
2023-10-05 10:26:10 +02:00
Matt Arsenault
59c6e2e9c1 InstCombine: Introduce SimplifyDemandedUseFPClass
This is the floating-point analog of SimplifyDemandedBits. If we know
the edge cases are assumed impossible in uses, it's possible to prune
upstream edge case handling.

Start by only using this on returns in functions with nofpclass
returns (where I'm surprised there are no other combines), but this
can be extended to include any other nofpclass use or FPMathOperator
with flags.

Partially addresses issue #64870

https://reviews.llvm.org/D158648
2023-10-04 21:06:24 -07:00
Jeremy Morse
d529943a27 [NFC][RemoveDIs] Prefer iterators over inst-pointers in InstCombine
As per my proposal for how to eliminate debug intrinsics [0], for various
places in InstCombine prefer to insert using an instruction iterator rather
than an instruction pointer. This is so that we can eventually pass more
information in the iterator class. These call-sites where I've changed the
spelling are those that necessary to build a stage2clang to produce an
identical binary in the coming no-debug-intrinsics mode.

[0] https://discourse.llvm.org/t/rfc-instruction-api-changes-needed-to-eliminate-debug-intrinsics-from-ir/68939

Differential Revision: https://reviews.llvm.org/D152543
2023-09-11 15:04:51 +01:00
Noah Goldstein
09b6765e7d [InstCombine] Remove trailing space in comment; NFC 2023-07-30 18:05:56 -05:00
Paulo Matos
eb5d79876a [InstCombine] Allow KnownBits to be propagated
Bug #63699 shows a hang on arm in instcombine because we do not
propagate known bits for fshl/fshr rotates. We perform the propagation
and add regression test.

Differential Revision: https://reviews.llvm.org/D155307
2023-07-18 13:01:22 +02:00
David Green
2802739dfd [NFC] Replace ;; with ; 2023-06-11 10:25:24 +01:00
Nikita Popov
fa45fb7f0c [InstCombine] Handle assumes in multi-use demanded bits simplification
This fixes the largest remaining discrepancy between results of
computeKnownBits() and SimplifyDemandedBits(). We only care about
the multi-use case here, because the assume necessarily introduces
an extra use.
2023-06-02 14:24:24 +02:00
Paulo Matos
9485d983ac [InstCombine] Disable generation of fshl/fshr for rotates
Disable conversion of funnel shifts (fshl/fshr) into rotates
unless one of the operands is known to be a constant value.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D150670
2023-06-01 15:31:49 +02:00
Nikita Popov
e1aa91b363 [InstCombine] Use KnownBits::shl() in SimplifyDemandedBits()
It is more precise than the custom logic we had. This came up when
trying to enforce a consistency assertion with computeKnownBits().
2023-05-26 14:43:10 +02:00
Nikita Popov
d3da5b4521 [InstCombine] Return poison for known bits conflict
I suspect that this case is not actually reachable in practice
(because it gets folded away by other code before), but if we do
reach it, we should return poison, not undef.
2023-05-17 18:40:12 +02:00
Nikita Popov
77aaba6aae [InstCombine] Compute bits of first operand for multi-use sub
Otherwise the result will always be unknown anyway. This fixes one
of the last inconsistencies in results between computeKnownBits()
and SimplifyDemandedBits().
2023-05-17 18:34:17 +02:00
Nikita Popov
745cfa3449 [InstCombine] Compute known bits for multi-use add/sub
We were failing to set the known bits for add/sub in the multi-use
case, resulting in odd behavioral differences depending on the
number of uses. Noticed while adding a consistency assertion.

The test changes are essentially a revert to the state before
d6498ab. These changes are not really desirable, but if we don't
want them, that needs to be handled as part of the heuristic for
demanded constant shrinking, not by artifically suppressing the
known bits in one specific case.
2023-05-17 17:50:00 +02:00
Nikita Popov
4ca30ded4f [InstCombine] Use KnownBits::urem() helper
This provides more precise results than the ad-hoc implementation.
Noticed while trying to add a consistency assertion.

To be honest I'm not sure why this code exists at all -- the
recursive calls are done with all bits demanded, so this should
be equivalent to just using the default case.
2023-05-17 17:14:54 +02:00
Nikita Popov
1bd2cc5f7b [InstCombine] Use KnownBits::udiv() helper
This produces more precise results than the ad-hoc implementation.

Noticed while trying to add a consistency assertion.
2023-05-17 17:03:35 +02:00
Nikita Popov
c557d3109a [InstCombine] Use computeKnownBits() for srem SimplifyDemandedBits()
For the case of a non-constant operand, fall back to
computeKnownBits() rather than trying to reimplement logic.

Found while testing a consistency assertion for both functions.
2023-05-17 15:57:23 +02:00