6 Commits

Author SHA1 Message Date
Scott Egerton
4a305d40a3
[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)
The s_singleuse_vdst instruction is used to mark regions of instructions
that produce values that have only one use.
Certain instructions take more than one cycle to execute, resulting in
regions being incorrectly marked.
This patch excludes these multi-cycle instructions from being marked as
either producing single use values or consuming single use values
or both depending on the instruction.
2024-06-12 10:43:23 +01:00
Simon Pilgrim
e47d7c6975 Fix MSVC signed/unsigned mismatch warning. NFC. 2024-05-03 09:38:51 +01:00
Scott Egerton
eb8236381b
[AMDGPU] Group multiple single use producers under one single use instruction. (#90713)
Previously each single use producer would be marked with a
"S_SINGLEUSE_VDST 1" instruction. This patch adds support for
larger immediates that encode multiple single use producers into
one S_SINGLEUSE_VDST instruction.
2024-05-02 17:30:11 +01:00
Scott Egerton
d97f25b948
[AMPGPU] Emit s_singleuse_vdst instructions when a register is used multiple times in the same instruction. (#89601)
Previously, multiple uses of a register within the same instruction were
being counted as multiple uses. This has been corrected to
only count as a single use as per the specification allowing for
more optimisation candidates.
2024-04-30 17:14:01 +01:00
Scott Egerton
af0b69f27d
[AMDGPU] Support wide register or subregister access when emitting s_singleuse_vdst instructions. (#88520)
Both single use producer and consumer instructions using wide/sub
registers are now correctly tracked and eligible for being marked as
single use.
2024-04-18 16:22:56 +01:00
Jay Foad
28233b11ac
[AMDGPU] New AMDGPUInsertSingleUseVDST pass (#72388)
Add support for emitting GFX11.5 s_singleuse_vdst instructions. This is
a power saving feature whereby the compiler can annotate VALU
instructions whose results are known to have only a single use, so the
hardware can in some cases avoid writing the result back to VGPR RAM.

To begin with the pass is disabled by default because of one missing
feature: we need an exclusion list of opcodes that never qualify as
single-use producers and/or consumers. A future patch will implement
this and enable the pass by default.

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Co-authored-by: Scott Egerton <scott.egerton@amd.com>
2023-11-24 10:23:06 +00:00