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Author	SHA1	Message	Date
Vikram Hegde	5feb32ba92	[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217 ) This patch is intended to be the first of a series with end goal to adapt atomic optimizer pass to support i64 and f64 operations (along with removing all unnecessary bitcasts). This legalizes 64 bit readlane, writelane and readfirstlane ops pre-ISel --------- Co-authored-by: vikramRH <vikhegde@amd.com>	2024-06-25 14:35:19 +05:30
Pierre van Houtryve	fcdb2203e0	[AMDGPU][AtomicOptimizer] Fix DT update for divergent values with Iterative strategy (#87605 ) We take the terminator from EntryBB and put it in ComputeEnd. Make sure we also move the DT edges, we previously only did it assuming a non-conditional branch. Fixes SWDEV-453943	2024-04-18 09:22:44 +02:00

Author

SHA1

Message

Date

Vikram Hegde

5feb32ba92

[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217 )

This patch is intended to be the first of a series with end goal to
adapt atomic optimizer pass to support i64 and f64 operations (along
with removing all unnecessary bitcasts). This legalizes 64 bit readlane,
writelane and readfirstlane ops pre-ISel

---------

Co-authored-by: vikramRH <vikhegde@amd.com>

2024-06-25 14:35:19 +05:30

Pierre van Houtryve

fcdb2203e0

[AMDGPU][AtomicOptimizer] Fix DT update for divergent values with Iterative strategy (#87605 )

We take the terminator from EntryBB and put it in ComputeEnd. Make sure
we also move the DT edges, we previously only did it assuming a
non-conditional branch.

Fixes SWDEV-453943

2024-04-18 09:22:44 +02:00

2 Commits