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19589 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
c0ecd1f7ed Corrects previously incorrect $sp change in MipsCompilationCallback. 
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

llvm-svn: 142930
 2011-10-25 17:30:47 +00:00
Jim Grosbach
17ec1a19e5 ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Dan Gohman
b43c36f391 Remove the Blackfin backend. 
llvm-svn: 142880
 2011-10-25 00:05:42 +00:00
Dan Gohman
dfc96aea90 Remove the SystemZ backend. 
llvm-svn: 142878
 2011-10-24 23:48:32 +00:00
Jim Grosbach
30c39c8bf2 Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. 
llvm-svn: 142877
 2011-10-24 23:40:46 +00:00
Jim Grosbach
92fd05ecdc ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Eli Friedman
a5e244c08d Don't crash on variable insertelement on ARM. PR10258. 
llvm-svn: 142871
 2011-10-24 23:08:52 +00:00
Evan Cheng
f33bfbbace ARMConstantPoolMBB::print should print BB number. 
llvm-svn: 142867
 2011-10-24 23:01:03 +00:00
Jim Grosbach
3ea0657d54 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

llvm-svn: 142861
 2011-10-24 22:16:58 +00:00
Jim Grosbach
2098cb1e6f ARM refactor am6offset usage for VLD1. 
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.

llvm-svn: 142853
 2011-10-24 21:45:13 +00:00
Eli Friedman
b72d55353a Add support to the old JIT for acquire/release loads and stores on x86. PR11207. 
llvm-svn: 142841
 2011-10-24 20:24:21 +00:00
Owen Anderson
295b1e84ce Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
llvm-svn: 142817
 2011-10-24 18:04:29 +00:00
Dan Gohman
4ed1afa51d Change this overloaded use of Sched::Latency to be an overloaded 
use of Sched::ILP instead, as Sched::Latency is going away.

llvm-svn: 142813
 2011-10-24 17:55:11 +00:00
Dan Gohman
2c9bda1512 Remove the explicit request for "Latency" scheduling from MSP430, 
as the Latency scheduler is going away.

llvm-svn: 142811
 2011-10-24 17:53:16 +00:00
Jim Grosbach
1b5e49a35a Thumb2 LDM instructions can target PC. Make sure to encode it. 
PR11220

llvm-svn: 142801
 2011-10-24 17:16:24 +00:00
Craig Topper
b05d9e9bea Add X86 SARX, SHRX, and SHLX instructions. 
llvm-svn: 142779
 2011-10-23 22:18:24 +00:00
Craig Topper
980d59832a Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper
e94d277db8 Add X86 MULX instruction for disassembler. 
llvm-svn: 142738
 2011-10-23 00:33:32 +00:00
Craig Topper
7412aa9886 Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions. 
llvm-svn: 142737
 2011-10-22 23:13:53 +00:00
Benjamin Kramer
0d6d098841 Move various generated tables into read-only memory, fixing up const correctness along the way. 
llvm-svn: 142726
 2011-10-22 16:50:00 +00:00
Nadav Rotem
e649d66552 Fix pr11193. 
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.

llvm-svn: 142724
 2011-10-22 12:39:25 +00:00
Bill Wendling
94e6643fce The different flavors of ARM have different valid subsets of registers. Check 
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2

llvm-svn: 142706
 2011-10-22 00:29:28 +00:00
Jim Grosbach
11c0b347c6 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach
118b38cbf1 Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
846bcff7c7 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
c4360fe575 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
2f2e3c4737 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Owen Anderson
03a173eb71 Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. 
llvm-svn: 142669
 2011-10-21 18:43:28 +00:00
Jim Grosbach
e6d88c9a51 Nuke an #if0 that got accidentally left in. 
llvm-svn: 142658
 2011-10-21 16:59:08 +00:00
Jim Grosbach
20cb505e2f whitespace. 
llvm-svn: 142657
 2011-10-21 16:56:40 +00:00
Jim Grosbach
e3013dd62d Remove some outdated comments. 
llvm-svn: 142653
 2011-10-21 16:14:12 +00:00
Craig Topper
039a79067a Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. 
llvm-svn: 142642
 2011-10-21 06:55:01 +00:00
Richard Smith
c842c2ffe2 Fix unused variable warning. 
llvm-svn: 142630
 2011-10-21 01:22:04 +00:00
Owen Anderson
16c8fc5191 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Dan Gohman
000e2add18 Disable the PPC hazard recognizer. It currently only supports 
top-down scheduling and top-down scheduling is going away.

llvm-svn: 142621
 2011-10-20 21:45:36 +00:00
Owen Anderson
3acac94b60 Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures. 
llvm-svn: 142618
 2011-10-20 21:24:38 +00:00
Bill Wendling
cf7bdf4438 Add missing operand. <rdar://problem/10313323> 
llvm-svn: 142615
 2011-10-20 20:37:11 +00:00
Lang Hames
aaf379027d Haven't yet found a nice way to handle TargetData verification in the 
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.

llvm-svn: 142605
 2011-10-20 19:24:44 +00:00
Jim Grosbach
79ebc51c45 Tidy up. Trailing whitespace. 
llvm-svn: 142591
 2011-10-20 17:28:20 +00:00
Jim Grosbach
9036c5cf2b ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach
8db25984a9 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Chad Rosier
add38c12b8 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
llvm-svn: 142557
 2011-10-20 00:07:12 +00:00
Evan Cheng
54d678fff4 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 
llvm-svn: 142550
 2011-10-19 22:22:54 +00:00
James Molloy
2d768fd379 Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530
 2011-10-19 14:11:07 +00:00
Bill Wendling
2977a15ab1 Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool. 
llvm-svn: 142485
 2011-10-19 09:24:02 +00:00
Bill Wendling
7c1634556d Remove some dead code. 
llvm-svn: 142484
 2011-10-19 09:04:11 +00:00
Craig Topper
ef309c3384 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
llvm-svn: 142480
 2011-10-19 07:48:35 +00:00
Bill Wendling
94f60018e0 Emit the MOVT instruction only if the # LPads is > 64K. 
llvm-svn: 142460
 2011-10-18 23:19:55 +00:00
Bill Wendling
64e6bfc16c For Thumb mode, we need to use a constant pool if the value is too large to be 
used with the CMP instruction.

llvm-svn: 142458
 2011-10-18 23:11:05 +00:00
Eric Christopher
16ec8c103a Revert "Turn on the vzeroupper pass by default." 
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

llvm-svn: 142455
 2011-10-18 23:10:11 +00:00