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847 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
c0ecd1f7ed Corrects previously incorrect $sp change in MipsCompilationCallback. 
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

llvm-svn: 142930
 2011-10-25 17:30:47 +00:00
Bruno Cardoso Lopes
2312a3aaa0 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Bill Wendling
2b7a1ff77f Coding style cleanups. No functionality change. 
llvm-svn: 142341
 2011-10-18 07:40:22 +00:00
Eli Friedman
4c42be5b32 Fix misc warnings. Patch by Joe Abbey. 
llvm-svn: 142332
 2011-10-18 03:17:34 +00:00
Akira Hatanaka
a7e0b90897 Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
 2011-10-17 18:53:29 +00:00
Akira Hatanaka
975bfc9b45 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00
Akira Hatanaka
3634f34659 Revert change made in r142205. 
llvm-svn: 142217
 2011-10-17 18:33:24 +00:00
Akira Hatanaka
33fe8f908c Redefine count-leading 0s and 1s instructions. 
llvm-svn: 142216
 2011-10-17 18:26:37 +00:00
Akira Hatanaka
8c446be204 Redefine mfhi/lo and mthi/lo instructions. 
llvm-svn: 142214
 2011-10-17 18:24:15 +00:00
Akira Hatanaka
0317b65367 Redefine multiply and divide instructions. 
llvm-svn: 142211
 2011-10-17 18:21:24 +00:00
Akira Hatanaka
2736bbc09e Add definition of a base class for logical shift/rotate instructions with two 
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
 2011-10-17 18:17:58 +00:00
Akira Hatanaka
73081309c3 Add definition of a base class for logical shift/rotate immediate instructions 
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
 2011-10-17 18:06:56 +00:00
Akira Hatanaka
e3f27b79dc Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. 
llvm-svn: 142205
 2011-10-17 18:01:00 +00:00
Akira Hatanaka
44419bfd54 Add f128 to datalayout string. 
llvm-svn: 141978
 2011-10-14 19:14:50 +00:00
Akira Hatanaka
62b34a65f9 Revert r141932, r141936 and r141937. 
llvm-svn: 141959
 2011-10-14 17:16:39 +00:00
Akira Hatanaka
d9ea7c8c31 Definition of function getMipsRegisterNumbering. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141938
 2011-10-14 03:04:24 +00:00
Akira Hatanaka
1742a2c093 Add definition of class MipsELFWriterInfo. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141937
 2011-10-14 02:55:47 +00:00
Akira Hatanaka
0fc7d7af5a Add missing relocation types. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141936
 2011-10-14 02:47:50 +00:00
Akira Hatanaka
769fc971b4 Fixup enumerations. 
Patch by Jack Carter at Mips. 

llvm-svn: 141934
 2011-10-14 02:38:56 +00:00
Akira Hatanaka
4e2bfe0770 Add more Mips relocation types. 
Patch by Jack Carter at Mips. 

llvm-svn: 141932
 2011-10-14 02:17:30 +00:00
Akira Hatanaka
3261c0fa6e Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. 
llvm-svn: 141761
 2011-10-12 01:05:13 +00:00
Akira Hatanaka
c57febff4a Fix encoding of 32-bit integer instructions. Change names of operands and nodes. 
Remove unused classes.

llvm-svn: 141757
 2011-10-12 00:56:06 +00:00
Akira Hatanaka
0f4ecf7548 Change name of class to ArithOverflowR. 
llvm-svn: 141743
 2011-10-11 23:43:48 +00:00
Akira Hatanaka
8f0d549c4c Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical 
instructions with two register operands derive from it.

llvm-svn: 141742
 2011-10-11 23:38:52 +00:00
Akira Hatanaka
8d4f74a6b1 Fix comment. 
llvm-svn: 141737
 2011-10-11 23:12:12 +00:00
Akira Hatanaka
ae5a9d6578 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit 
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
 2011-10-11 23:05:46 +00:00
Akira Hatanaka
1c18465859 Fix function isUnalignedLoadStore. 
llvm-svn: 141722
 2011-10-11 22:04:01 +00:00
Akira Hatanaka
10ae11fd57 Remove unused PatLeaf. 
llvm-svn: 141720
 2011-10-11 21:53:08 +00:00
Akira Hatanaka
453ac88b56 Change the names of 64-bit logical instructions so that they match the names of 
the real instructions.

llvm-svn: 141718
 2011-10-11 21:48:01 +00:00
Akira Hatanaka
46a7994ac9 Remove redundancy in setcc patterns using multiclass. 
llvm-svn: 141715
 2011-10-11 21:40:01 +00:00
Akira Hatanaka
8c1c51045d Use sltiu instead of sltu when a register operand and immediate are compared. 
llvm-svn: 141708
 2011-10-11 20:44:43 +00:00
Akira Hatanaka
7148bce86e Add patterns for conditional branches with 64-bit register operands. 
llvm-svn: 141696
 2011-10-11 19:09:09 +00:00
Akira Hatanaka
f75add6236 Add support for 64-bit set-on-less-than instructions. 
llvm-svn: 141695
 2011-10-11 18:53:46 +00:00
Akira Hatanaka
4b6ac98fcf Add support for conditional branch instructions with 64-bit register operands. 
llvm-svn: 141694
 2011-10-11 18:49:17 +00:00
Akira Hatanaka
b6d72cbeb9 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
 2011-10-11 01:12:52 +00:00
Akira Hatanaka
09b23eb7bc Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Akira Hatanaka
fa55bc27cb Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. 
llvm-svn: 141615
 2011-10-11 00:44:20 +00:00
Akira Hatanaka
e6ced5b3d5 Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. 
llvm-svn: 141613
 2011-10-11 00:37:28 +00:00
Akira Hatanaka
be68f3c348 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Akira Hatanaka
fd2d7dcc31 Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
 2011-10-11 00:11:12 +00:00
Akira Hatanaka
6be7d6c976 Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00
Akira Hatanaka
2365f90676 Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka
c7548dec7d Define multiclasses for FP-to-FP instructions. 
llvm-svn: 141474
 2011-10-08 03:29:22 +00:00
Akira Hatanaka
13ae13bdc2 Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Akira Hatanaka
557c8e3443 Add patterns for unaligned load and store instructions and enable the 
instruction selector to generate them.

llvm-svn: 141471
 2011-10-08 02:24:10 +00:00
Peter Collingbourne
fb3d935649 Build system infrastructure for multiple tblgens. 
llvm-svn: 141266
 2011-10-06 01:51:51 +00:00
Akira Hatanaka
c6b742f98a Fix assertion string. 
llvm-svn: 141197
 2011-10-05 18:17:49 +00:00
Akira Hatanaka
426a804825 Make sure candidate for delay slot filler is not a return instruction. 
llvm-svn: 141196
 2011-10-05 18:16:09 +00:00
Akira Hatanaka
14e4149f4e Add RA to the set of registers that are defined if instruction is a call. 
llvm-svn: 141194
 2011-10-05 18:11:44 +00:00
NAKAMURA Takumi
9ebdf46b5a MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly. 
llvm-svn: 141174
 2011-10-05 10:11:02 +00:00