112236 Commits

Author SHA1 Message Date
Brandon Wu
c81e5faa6f
[RISCV] Add CFI information for vector callee-saved registers (#86811)
Currently the CFI offset for RVV registers are not handled entirely,
this patch add those information for either stack unwinding or
debugger to work correctly on RVV callee-saved stack object.

Depends On D154576

Differential Revision: https://reviews.llvm.org/D156846
2024-04-17 10:42:40 +08:00
Michael Liao
62853a246e [TableGen][InstrInfoEmitter] Count sub-operands on def operands
- If a def operand includes multiple sub-operands, count them when
  generating instr info.
- Found issues in x86 and sparc backends, where memory operands of
  store or store-like instructions are wrongly placed in the output
  list.

Reviewers: jayfoad, arsenm, Pierre-vh

Reviewed By: arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/88972
2024-04-16 20:34:20 -04:00
Nikita Popov
efd60556f7 Revert "[SLP]Attempt to vectorize long stores, if short one failed."
This reverts commit 7d4e8c1f3bbfe976f4871c9cf953f76d771b0eda.

Contrary to the commit description, this does cause large
compile-time regressions (up to 10% on individual files).
2024-04-17 09:25:05 +09:00
Andy Kaylor
be50a259f1
Update foldFMulReassoc to respect absent fast-math flags (#88589)
This change updates a few of the transformations in foldFMulReassoc to
respect absent fast-math flags in cases where fmul and fdiv, fadd, or fsub
instructions were being folded but the code was only checking for
fast-math flags on the fmul instruction and was transferring flags to
the folded instruction that were not present on the other original 
instructions.

This fixes https://github.com/llvm/llvm-project/issues/82857
2024-04-16 16:22:31 -07:00
Craig Topper
9067070d91
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
This is largely a revert of commit
e81796671890b59c110f8e41adc7ca26f8484d20.

As #88029 shows, there exists hardware that only supports unaligned
scalar.

I'm leaving how this gets exposed to the clang interface to a future
patch.
2024-04-16 15:40:32 -07:00
Noah Goldstein
9eeae44211 [ValueTracking] Implement computeKnownFPClass for llvm.vector.reduce.{fmin,fmax,fmaximum,fminimum}
Closes #88408
2024-04-16 16:10:00 -05:00
Noah Goldstein
266b2a2640 [ValueTracking] Add tests for computeKnownFPClass of llvm.vector.reduce.{fmin,fmax,fmaximum,fminimum}; NFC 2024-04-16 16:10:00 -05:00
Arthur Eubanks
c6e01627ac Revert "Reapply "[LV] Improve AnyOf reduction codegen. (#78304)""
This reverts commit c6e38b928c56f562aea68a8e90f02dbdf0eada85.

Causes miscompiles, see comments on #78304.
2024-04-16 20:40:21 +00:00
Philip Reames
885b8d9bb5 [RISCV] Enable mul strength reduction for XTheadBa
This vendor extension has the same shift_add as zba, and most of the same
patterns are duplicated.  Enable it here too so the configurations don't
diverge.
2024-04-16 13:28:11 -07:00
Noah Goldstein
b6bd41db31 [InstCombine] Add canonicalization of sitofp -> uitofp nneg
This is essentially the same as #82404 but has the `nneg` flag which
allows the backend to reliably undo the transform.

Closes #88299
2024-04-16 15:26:25 -05:00
Florian Hahn
34777c238b
[VPlan] Don't mark VPBlendRecipe as phi-like.
VPBlendRecipes don't get lowered to phis and usually do not appear at
the beginning of blocks, due to their masks appearing before them.

This effectively relaxes an over-eager verifier message.

Fixes https://github.com/llvm/llvm-project/issues/88297.
Fixes https://github.com/llvm/llvm-project/issues/88804.
2024-04-16 21:24:25 +01:00
Nicolai Hähnle
e770249d95 update_test_checks: add new test
This test is meant to demonstrate an upcoming change that replaces basic
block labels by FileCheck patterns.
2024-04-16 22:04:33 +02:00
Nicolai Hähnle
191be2a8a8 update_test_checks: pre-commit a new test
The test shows that name preservation doesn't work properly when
--include-generated-funcs is used.
2024-04-16 22:00:14 +02:00
Arthur Eubanks
281d71604f
[X86] Change how we treat functions with explicit sections as small/large (#88172)
Following #78348, we should treat functions with an explicit section as
small, unless the section name is (or has the prefix) ".ltext".

Clang emits global initializers into a ".text.startup" section on Linux.
If we mix small/medium code model object files with large code model
object files, we'll end up mixing sections with and without the large
section flag.

Reland of #87838 with a check for non-ELF platforms in
TargetMachine::isLargeGlobalValue(), otherwise MCJIT on Windows tests
fail.
2024-04-16 12:48:04 -07:00
Alexey Bataev
7d4e8c1f3b
[SLP]Attempt to vectorize long stores, if short one failed.
We can try to vectorize long store sequences, if short ones were
unsuccessful because of the non-profitable vectorization. It should not
increase compile time significantly (stores are sorted already,
complexity is n x log n), but vectorize extra code.

Metric: size..text

Program                                                                         size..text
                                                                                results     results0    diff
         test-suite :: External/SPEC/CINT2006/400.perlbench/400.perlbench.test  1088012.00  1088236.00  0.0%
                  test-suite :: SingleSource/UnitTests/matrix-types-spec.test   480396.00   480476.00  0.0%
          test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test   664613.00   664661.00  0.0%
         test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test   664613.00   664661.00  0.0%
        test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test  2041105.00  2040961.00 -0.0%
                 test-suite :: MultiSource/Applications/JM/lencod/lencod.test   836563.00   836387.00 -0.0%
                 test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test  1035100.00  1032140.00 -0.3%

In all benchmarks extra code gets vectorized

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/88563
2024-04-16 14:55:41 -04:00
Alexey Bataev
c7657cf7d1
[SLP]Keep externally used GEPs as GEPs, if possible instead of extractelement.
If the vectorized GEP instruction can be still kept as a scalar GEP,
better to keep it as scalar instead of extractelement. In many cases it
is more profitable.

Metric: size..text

Program                                                                          size..text
                                                                                 results     results0    diff
                        test-suite :: SingleSource/Benchmarks/Misc/oourafft.test    18911.00    19695.00  4.1%
                   test-suite :: SingleSource/Benchmarks/Misc-C++-EH/spirit.test    59987.00    60707.00  1.2%
       test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test  1392209.00  1392753.00  0.0%
        test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test  1392209.00  1392753.00  0.0%
           test-suite :: External/SPEC/CINT2006/400.perlbench/400.perlbench.test  1087996.00  1088236.00  0.0%
                         test-suite :: MultiSource/Benchmarks/Bullet/bullet.test   309310.00   309342.00  0.0%
             test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test   664661.00   664693.00  0.0%
            test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test   664661.00   664693.00  0.0%
        test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 12354636.00 12354908.00  0.0%
                  test-suite :: External/SPEC/CFP2006/453.povray/453.povray.test  1152748.00  1152716.00 -0.0%
                       test-suite :: MultiSource/Applications/oggenc/oggenc.test   191787.00   191771.00 -0.0%
                     test-suite :: SingleSource/UnitTests/matrix-types-spec.test   480796.00   480476.00 -0.1%

Misc/oourafft - Extra code gets vectorized
Misc-C++-EH/spirit - same
CFP2017speed/638.imagick_s
CFP2017rate/538.imagick_r - same, extra code gets vectorized
CINT2006/400.perlbench - some extra 4 x ptr stores vectorized
Bullet/bullet - extra 4 x ptr store vectorized
CINT2017rate/525.x264_r
CINT2017speed/625.x264_s - same
CFP2017rate/526.blender_r - extra 8 x float stores (several), some extra
4 x ptr stores
CFP2006/453.povray - 2 x double loads/stores replaced by 4 x double
loads/stores
Applications/oggenc - extra code is vectorized
UnitTests/matrix-types-spec - extra code gets vectorized

Reviewers: RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/88877
2024-04-16 14:54:06 -04:00
Philip Reames
bbd64c4ddf [RISCV] Add coverage for strength reduction of mul as 2^N - 2^M 2024-04-16 11:46:27 -07:00
Noah Goldstein
edb711d2f3 [InstCombine] Update vector_reduce_and tests to actually use llvm.vector.reduce.and; NFC 2024-04-16 13:36:20 -05:00
Philip Reames
6b83fe5529
[RISCV] Strength reduce mul by 2^n + 2/4/8 + 1 (#88911)
With zba, we can expand this to (add (shl X, C1), (shXadd X, X)).

Note that this is our first expansion to a three instruction sequence. I
believe this to general be a reasonable tradeoff for most architectures,
but we may want to (someday) consider a tuning flag here.

I plan to support 2^n + (2/4/8 + 1) eventually as well, but that comes
behind 2^N - 2^M. Both are also three instruction sequences.

---------

Co-authored-by: Min-Yih Hsu <min@myhsu.dev>
2024-04-16 11:03:53 -07:00
Philip Reames
184ba038ac
[RISCV] Avoid matching 3/5/9 * 2^N as 2^N + 2/4/8 (e.g. 24) (#88937)
The former is better as a zero extend can be folded into the sll,
whereas the later currently produces a seperate zext.w due to bad
interactions with other combines.
2024-04-16 10:46:27 -07:00
Stephen Tozer
1c6b0f779f
[RemoveDI] Add support for debug records to debugify (#87383)
This patch changes debugify to support debug variable records, and
subsequently to no longer convert modules automatically to intrinsics
when entering debugify.
2024-04-16 17:07:46 +01:00
Simon Pilgrim
bf1ad1d267 [VectorCombine][X86] Add initial shuffle-of-shuffles.ll test cover for #88743 2024-04-16 16:11:09 +01:00
Philip Reames
bd28889732 [RISCV] Add coverage for strength reduction of mul 2^N +/- 3/5/9 2024-04-16 07:59:26 -07:00
XChy
d2d4a1bbdc
Revert "[JumpThreading] Thread over BB with only an unconditional branch" (#88907)
Reverts llvm/llvm-project#86312
2024-04-16 22:52:19 +08:00
Simon Pilgrim
254df2e35c [VectorCombine][X86] shuffle-of-binops.ll - split off foldShuffleOfBinops tests from shuffle.ll 2024-04-16 14:52:24 +01:00
Alexey Bataev
e84b2fb48d
[LV][NFCI]Use integer for cost/trip count calculations instead of double, fix possible UB.
Using fp type in the compiler is not the best idea, here it used with
the comparison for equal to 0 and may cause undefined behavior in some
cases.

Reviewers: fhahn

Reviewed By: fhahn

Pull Request: https://github.com/llvm/llvm-project/pull/87241
2024-04-16 09:48:13 -04:00
Simon Pilgrim
e185978321 [VectorCombine][X86] Regenerate shuffle.ll + shuffle-of-casts.ll
Use v4 of UTC to improve regex matching of argument names to fix a filecheck matching in a future patch
2024-04-16 14:46:30 +01:00
Alexey Bataev
26ebe16d78 [SLP]Fix PR88834: check if unsigned arg can be trunced, being used in smax/smin intrinsics.
Need to check that unsigned argument can be safely used in smax/smin
intrinsics by checking if at least single sign bit is cleared, otherwise
its value may be treated as negative instead of positive.
2024-04-16 06:42:15 -07:00
Alexey Bataev
6ab5927238 [SLP][NFC]Add a test with the incorrect vectorization of smax with unsigned arg. 2024-04-16 06:35:13 -07:00
Shilei Tian
9ce74d6d47
[AMDGPU][CodeGen] Improve handling of memcpy for -Os/-Oz compilations (#87632)
We had some instances when LLVM would not inline fixed-count memcpy and
ended up
attempting to lower it a a libcall, which would not work on AMDGPU as
the
address space doesn't meet the requirement, causing compiler crash.

The patch relaxes the threshold used for -Os/-Oz compilation so we're
always allowed
to inline memory copy functions.

This patch basically does the same thing as
https://reviews.llvm.org/D158226 for
AMDGPU.

Fix #88497.
2024-04-16 09:34:18 -04:00
Florian Hahn
b73476c784
[SLP] Make sure MinVF is a power-of-2 by using PowerOf2Ceil.
This should ensure we explore the same VFs as before 6d66db3890a18e39.

Fixes https://github.com/llvm/llvm-project/issues/88640.
2024-04-16 13:29:35 +01:00
Simon Pilgrim
34013e7ce2 [X86] Add shuffle tests for BLEND(PERMUTE(X),PERMUTE(Y)) patterns
Some very basic tests for a case where we could fold BLEND(PERMUTE(X),PERMUTE(Y)) -> PERMUTE(BLEND(X,Y))

These assume the permute masks are the same, and "complete" (no undefs/duplicate elements) but we could relax that depending on the blend mask
2024-04-16 13:27:12 +01:00
Brandon Wu
91dd844aa4
Recommit [RISCV] RISCV vector calling convention (2/2) (#79096) (#87736)
Bug fix: Handle RVV return type in calling convention correctly.
Return values are handled in a same way as function arguments.
One thing to mention is that if a type can be broken down into
homogeneous
vector types, e.g. {<vscale x 4 x i32>, {<vscale x 4 x i32>, <vscale x 4
x i32>}},
it is considered as a vector tuple type and need to be handled by tuple
type rule.
2024-04-16 19:59:36 +08:00
Simon Pilgrim
c18a3b6bd3 [DAG] Fold extract_subvector(insert_subvector(x,y,c1),c2) --> extract_subvector(y,c2-c1) (#87925) (REAPPLIED)
If the extract_subvector is cheap, attempt to extract directly from an inserted subvector

Reapplied with a check to ensure we only attempt this for fixed vectors
2024-04-16 12:30:27 +01:00
Jon Chesterfield
ac6b4c618a Reapply "[Verifier] Reject va_start in non-variadic function (#88809)"
This reverts commit f4960da6023b8034ae68925c3223d51624621b37.
Includes a fix for the MLIR test case.
2024-04-16 12:26:08 +01:00
Malay Sanghi
92e96c7bba
[X86][GISel] Add DU chain lookups for LOAD & STORE (#87453)
For G_LOAD and G_STORE we want this information during regbankselect.
Today we treat load dest as integer and insert converts.

---------

Co-authored-by: Evgenii Kudriashov <evgenii.kudriashov@intel.com>
2024-04-16 13:06:17 +02:00
XChy
36b3c26451
[JumpThreading] Thread over BB with only an unconditional branch (#86312)
Fixes #76609
This patch does:
- relax the phis constraint in `CanRedirectPredsOfEmptyBBToSucc`
- guarantee the BB has multiple different predecessors to redirect, so
that we can handle the case without phis in BB. Without this change and
phi constraint, we may redirect the CommonPred.

The motivation is consistent with JumpThreading. We always want the
branch to jump more direct to the destination, without passing the
middle block. In this way, we can expose more other optimization
opportunities.

An obivous example proposed by @dtcxzyw is like:
```llvm
define i32 @test(...) {
entry:
   br i1 %c, label %do.end, label %if.then

if.then:                                          ; preds = %entry
   %call2 = call i32 @dummy()
   %tobool3.not = icmp eq i32 %call2, 0
   br i1 %tobool3.not, label %do.end, label %return

do.end:                                           ; preds = %entry, %if.then
   br label %return

return:                                           ; preds = %if.then, %do.end
   %retval.0 = phi i32 [ 0, %do.end ], [ %call2, %if.then ]
   ret i32 %retval.0
}
```
`entry` can directly jump to return, without passing `do.end`, and then
the if-else pattern can be simplified further:
```llvm
define i32 @test(...) {
entry:
   br i1 %c, label %return, label %if.then

if.then:                                          ; preds = %entry
   %call2 = call i32 @dummy()
   br label %return

return:                                           ; preds = %if.then
   %retval.0 = phi i32 [ 0, %entry ], [ %call2, %if.then ]
   ret i32 %retval.0
}
```
2024-04-16 18:51:03 +08:00
Jinyang He
01f79899ba
[LoongArch] Use R_LARCH_ALIGN with section symbol (#84741)
In LoongArch psABI v2.30, the R_LARCH_ALIGN requires symbol index to
support the third parameter of alignment directive. Create symbol for
each section is redundant because they have section symbol which can
also be used as symbol index. So use section symbol directly for
R_LARCH_ALIGN.
2024-04-16 18:31:03 +08:00
Jon Chesterfield
f4960da602 Revert "[Verifier] Reject va_start in non-variadic function (#88809)"
This reverts commit 61717c1aa1f08eb57839a21fb2d9004739022e0d. Failed a MLIR test
2024-04-16 11:24:45 +01:00
choikwa
422bf13f33
[AMDGPU] In VectorLegalizer::Expand, if UnrollVectorOp returns Load, … (#88475)
…return only Load since other output is chain.

Added testcase that showed mismatched expected arity when Load and chain
were returned as separate items after
003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d
2024-04-16 06:04:37 -04:00
Jon Chesterfield
61717c1aa1
[Verifier] Reject va_start in non-variadic function (#88809)
A va_start intrinsic lowers to something derived from the variadic
parameter to the function. If there is no such parameter, it can't lower
meaningfully. Clang sema rejects the same with `error: 'va_start' used
in function with fixed args`.

Moves the existing lint warning into a verifier error. Updates the one
lit test that had a va_start in a non-variadic function.
2024-04-16 10:33:54 +01:00
Yingwei Zheng
80fce05f21
[InstCombine] Fold minmax (X & NegPow2C, Y & NegPow2C) -> minmax(X, Y) & NegPow2C (#88859)
Alive2: https://alive2.llvm.org/ce/z/NFtkSX

This optimization will be beneficial to jemalloc users.
2024-04-16 17:16:35 +08:00
Jay Foad
f4f772ceef
[AMDGPU] Stop reserving $vcc_hi in wave32 mode (#87783)
This gives us one extra SGPR to play with. The comment suggested that it
could cause bugs, but I have tested it with Vulkan CTS with the default
wave size for compute shaders set to 32 and did not find any problems.
2024-04-16 10:15:00 +01:00
Jay Foad
4fc0a99b8f
[AMDGPU] Fix implicit operands of VOPD cndmask instructions (#87788) 2024-04-16 10:14:15 +01:00
Carlos Alberto Enciso
66cf995da7
[IPSCCP] Variable not visible at Og: (#77901)
https://bugs.llvm.org/show_bug.cgi?id=51559
https://github.com/llvm/llvm-project/issues/50901

IPSCCP pass removes the global variable and does not create a constant
expression for the initializer value.

Extend test coverage to include:
- half, bfloat types.
- checks for undef (int32 and ptr).

There is no support for:
- fp128, x86_fp80, ppc_fp128  types.
https://github.com/llvm/llvm-project/issues/88102
2024-04-16 09:37:51 +01:00
Pengcheng Wang
dbaa1893c9
[RISCV] Generate more W instructons
We rename `TuneNoStripWSuffix` to `TunePreferWInst`.

If all the users of an instruction just use the low 32 bits, we can
convert it to its W variant.

A quick test on Coremark (`-O3 -march=rv64gc`):

|        | W instructions | code size(.text) |
|--------|----------------|------------------|
| before | 302            | 12257            |
| after  | 343            | 12265            |
|        | +13.58%        | +0.065%          |

Reviewers: asb, dtcxzyw, preames, lukel97, michaelmaitland, topperc

Reviewed By: topperc, dtcxzyw

Pull Request: https://github.com/llvm/llvm-project/pull/87237
2024-04-16 15:37:31 +08:00
darkbuck
e2c91091e5
[GlobalISel] Handle more commutable instructions in commute_constant_to_rhs
Reviewers:
rupprecht, aartbik, cyndyishida, Pierre-vh, aemerson, ftynse, hanhanW, banach-space, jayfoad, nicolasvasilache, daniel-grumberg, arsenm, PeimingLiu, JDevlieghere, matthias-springer

Reviewed By: arsenm, Pierre-vh

Pull Request: https://github.com/llvm/llvm-project/pull/87424
2024-04-16 02:36:12 -04:00
Craig Topper
17d6bf046c
[RISCV] Change how MMO is rebuilt in lowerFixedLengthVectorLoadToRVV/lowerFixedLengthVectorStoreToRVV (#88811)
Copy the pointer info, flags, alignment, AAInfo, and ranges, but let
getLoad rebuild the MMO using the scalable type used for the the new
load/store. This makes sure the LLT minimum size matches the ContainerVT
minimum size. This is important since vscale_range may have been used to
determine that the fixed vector was the exact size of a scalable vector.

Fixes #88799
2024-04-15 22:39:09 -07:00
Craig Topper
f14146fd46
[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)
The instruction names should be c.mop.1 instead of cmop.1.
2024-04-15 22:33:14 -07:00
Vlad Mishel
edb0708dc1
[InstCombine] Implement fcmp (fadd x, 0.0), y => fcmp x, y optimization (#88476)
This PR addresses issue #88168. It implements an optimization for
the case of

```
define i1 @fcmp_fadd_zero_ugt(float %x, float %y) {
  %add = fadd float %x, 0.000000e+00
  %cmp = fcmp ugt float %add, %y
  ret i1 %cmp
}
```
`=>`
```
define i1 @fcmp_fadd_zero_ugt(float %x, float %y) {
  %cmp = fcmp ugt float %x, %y
  ret i1 %cmp
}
```
and all other types of `fcmp` instructions (`uge`, `ogt`, etc).

Proofs: 
`fadd x, 0.0` https://alive2.llvm.org/ce/z/7FzNnM
`fsub x, 0.0` https://alive2.llvm.org/ce/z/puUxLK
2024-04-16 13:05:29 +08:00