Christudasan Devadasan
230c13d59d
[AMDGPU] Pick available high VGPR for CSR SGPR spilling ( #78669 )
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CSR SGPR spilling currently uses the early available physical VGPRs. It
currently imposes a high register pressure while trying to allocate
large VGPR tuples within the default register budget.
This patch changes the spilling strategy by picking the VGPRs in the
reverse order, the highest available VGPR first and later after regalloc
shift them back to the lowest available range. With that, the initial
VGPRs would be available for allocation and possibility
of finding large number of contiguous registers will be more.
2024-01-24 07:08:43 +05:30
Matt Arsenault
af4f1766ae
AMDGPU: Allocate special SGPRs before user SGPR arguments ( #78234 )
2024-01-17 21:41:50 +07:00
Saiyedul Islam
777b6de7a4
[AMDGPU][NFC] Test autogenerated llc tests for COV5 ( #74339 )
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Regenerate a few llc tests to test for COV5 instead of the default ABI
version.
2023-12-12 14:35:13 +05:30
Saiyedul Islam
466a8149b3
Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 ( #65410 )" ( #66060 )
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This reverts commit 0a8d17e79b02a92814a2a788d79df1f54d70ec3e.
2023-09-12 15:13:59 +05:30
Saiyedul Islam
0a8d17e79b
[AMDGPU] Make default AMDHSA Code Object Version to be 5 ( #65410 )
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Also update LIT tests and docs.
For more details, see
https://llvm.org/docs/AMDGPUUsage.html#code-object-v5-metadata
Reviewed By: arsenm, jhuber6
Github PR: #65410
Differential Revision: https://reviews.llvm.org/D129818
2023-09-12 13:53:31 +05:30
Matt Arsenault
def228553c
AMDGPU: Use pown instead of pow if known integral
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https://reviews.llvm.org/D158998
2023-09-01 08:22:16 -04:00
Matt Arsenault
deefda7074
AMDGPU: Use exp2 and log2 intrinsics directly for f16/f32
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These codegen correctly but f64 doesn't. This prevents losing fast
math flags on the way to the underlying intrinsic.
https://reviews.llvm.org/D158997
2023-09-01 08:22:16 -04:00
Matt Arsenault
dac8f974b5
AMDGPU: Handle sitofp and uitofp exponents in fast pow expansion
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https://reviews.llvm.org/D158996
2023-09-01 08:22:16 -04:00
Matt Arsenault
aa539b128f
AMDGPU: Add baseline tests for libcall recognition of pow/powr/pown
2023-08-30 10:10:03 -04:00
