14 Commits

Author SHA1 Message Date
Alina Sbirlea
29e5c1c927 [Hexagon] Fix test after 9d7df23f4d6537752854d54b0c4c583512b930d0 2025-01-10 13:03:28 -08:00
Santanu Das
9d7df23f4d
[Hexagon] Add missing pattern for v8i1 type (#120703)
HexagonISD::PFALSE and PTRUE patterns do not form independently in
general as they are treated like operands of all 0s or all 1s. Eg: i32 =
transfer HEXAGONISD::PFALSE.
In this case, v8i1 = HEXAGONISD::PFALSE is formed independently without
accompanying opcode.

This patch adds a pattern to transfer all 0s or all 1s to a scalar
register and then use that register and this PFALSE/PTRUE opcode to
transfer to a predicate register like v8i1.
2025-01-10 09:54:02 -06:00
Fangrui Song
2208c97c1b [Hexagon,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449

-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.

Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.
2024-12-15 10:20:22 -08:00
Sumanth Gundapaneni
aaf2d078b6
[Hexagon] Clean up redundant transfer instructions. (#82663)
This patch adds a Hexagon specific backend pass that cleans up redundant
transfers after register allocation.
2024-02-22 17:31:37 -06:00
Konstantina Mitropoulou
2c5d1b5ab7 [DAGCombiner] Reassociate the operands from (OR (OR(CMP1, CMP2)), CMP3) to (OR (OR(CMP1, CMP3)), CMP2)
This happens when CMP1 and CMP3 have the same predicate (or CMP2 and CMP3 have
the same predicate).

This helps optimizations such as the fololowing one:
CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C)
CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C)

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D156215
2023-08-08 20:08:01 -07:00
Krzysztof Parzyszek
5ad9adb9b0 [Hexagon] Add missing patterns for boolean [v]selects
Fixes https://github.com/llvm/llvm-project/issues/59663
2023-06-17 17:15:07 -07:00
Krzysztof Parzyszek
833438eef0 [Hexagon] Handle all compares of i1 and vNi1
Fixes https://github.com/llvm/llvm-project/issues/63363
2023-06-17 16:31:21 -07:00
Krzysztof Parzyszek
d1c3ec61d6 [Hexagon] Add missing patterns for truncate to vNi1 2023-06-17 16:31:21 -07:00
Nikita Popov
a96f691985 [Hexagon] Convert some tests to opaque pointers (NFC) 2022-12-19 12:53:32 +01:00
Ikhlas Ajbar
4bb6e220a0 [Hexagon] Add missing patterns for select
Fixes https://github.com/llvm/llvm-project/issues/59077.
2022-11-22 12:20:38 -08:00
Krzysztof Parzyszek
ea6693d4c8 [Hexagon] Add missing patterns for mulhs/mulhu 2022-11-18 08:13:57 -08:00
Krzysztof Parzyszek
9c5ed8d567 [Hexagon] Add patterns to load i1
This fixes https://llvm.org/PR50853
2021-06-28 12:17:30 -05:00
Krzysztof Parzyszek
06234f758e [Hexagon] Improve lowering of returns of i1
Emit explicit any-extend to avoid weird tstbit sequences.
2021-04-22 16:47:52 -05:00
Krzysztof Parzyszek
ab9521aaeb [Hexagon] Use 'vnot' instead of 'not' in patterns with vectors
'not' expands to checking for an xor with a -1 constant. Since
this looks for a ConstantSDNode it will never match for a vector.

Co-authored-by: Craig Topper <craig.topper@sifive.com>

Differential Revision: https://reviews.llvm.org/D100687
2021-04-22 15:36:20 -05:00