7 Commits

Author SHA1 Message Date
Bing1 Yu
56d5c46b49 [X86] Support __tile_stream_loadd intrinsic for new AMX interface
Adding support for __tile_stream_loadd intrinsic.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D103784
2021-06-11 17:28:43 +08:00
Xiang1 Zhang
d4bdeca576 [X86] Support AMX fast register allocation
Differential Revision: https://reviews.llvm.org/D100026
2021-05-08 14:21:11 +08:00
Xiang1 Zhang
bebafe01a7 Revert "[X86] Support AMX fast register allocation"
This reverts commit 77e2e5e07d01fe0b83c39d0c527c0d3d2e659146.
2021-05-08 13:43:32 +08:00
Xiang1 Zhang
77e2e5e07d [X86] Support AMX fast register allocation 2021-05-08 13:27:21 +08:00
Benjamin Kramer
df323ba445 Revert "[X86] Support AMX fast register allocation"
This reverts commit 3b8ec86fd576b9808dc63da620d9a4f7bbe04372.

Revert "[X86] Refine AMX fast register allocation"

This reverts commit c3f95e9197643b699b891ca416ce7d72cf89f5fc.

This pass breaks using LLVM in a multi-threaded environment by
introducing global state.
2021-04-29 18:56:33 +02:00
Xiang1 Zhang
c3f95e9197 [X86] Refine AMX fast register allocation 2021-04-25 14:20:53 +08:00
Xiang1 Zhang
3b8ec86fd5 [X86] Support AMX fast register allocation
Differential Revision: https://reviews.llvm.org/D100026
2021-04-25 09:45:41 +08:00