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4 Commits

Author SHA1 Message Date
Petar Avramovic
b082e6f88a [AMDGPU] Extend gfx10 test coverage. NFC. 
Differential Revision: https://reviews.llvm.org/D99267
 2021-03-29 11:13:55 +02:00
Matt Arsenault
f9a42ed0a7 AMDGPU: Relax 32-bit SGPR register class 
Mostly use SReg_32 instead of SReg_32_XM0 for arbitrary values. This
will allow the register coalescer to do a better job eliminating
copies to m0.

For GlobalISel, as a terrible hack, use SGPR_32 for things that should
use SCC until booleans are solved.

llvm-svn: 375267
 2019-10-18 18:26:37 +00:00
Matt Arsenault
eb6eb694e4 AMDGPU/GlobalISel: Allow selection of scalar min/max 
I believe all of the uniform/divergent pattern predicates are
redundant and can be removed. The uniformity bit already influences
the register class, and nothhing has broken when I've removed this and
others.

llvm-svn: 372450
 2019-09-21 02:37:33 +00:00
Matt Arsenault
01bb075c1f GlobalISel: Add GINodeEquiv for min/max 
llvm-svn: 364759
 2019-07-01 13:22:04 +00:00