shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
26,527 Commits 1,712 Branches 298 Tags
Commit Graph

80 Commits

Author SHA1 Message Date
Rafael Espindola
f7d4a9900c Implement a MachineFunctionPass to fix the mul instruction 
llvm-svn: 30485
 2006-09-19 15:49:25 +00:00
Rafael Espindola
3130a756ef add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Evan Cheng
9a083a4121 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Rafael Espindola
c7829d62c0 implement SRL and MUL 
llvm-svn: 30262
 2006-09-11 19:24:19 +00:00
Rafael Espindola
bccf9c2f1b add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
llvm-svn: 30261
 2006-09-11 19:23:32 +00:00
Rafael Espindola
e45a79a9e2 partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola
ecb0d686f8 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization 
llvm-svn: 30246
 2006-09-11 12:49:38 +00:00
Anton Korobeynikov
fbee8bfe48 Removed unnecessary Mangler creation. 
llvm-svn: 30239
 2006-09-10 21:17:03 +00:00
Rafael Espindola
d11fb5d13b implement shl and sra 
llvm-svn: 30191
 2006-09-08 17:36:23 +00:00
Rafael Espindola
4443c7d60a add the eor (xor) instruction 
llvm-svn: 30189
 2006-09-08 16:59:47 +00:00
Rafael Espindola
778769aafb implement unconditional branches 
fix select.ll

llvm-svn: 30186
 2006-09-08 12:47:03 +00:00
Jim Laskey
ae92ce8798 1. Remove condition on delete. 
2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.

llvm-svn: 30169
 2006-09-07 23:39:26 +00:00
Jim Laskey
261779bb45 Make target asm info a property of the target machine. 
llvm-svn: 30162
 2006-09-07 22:06:40 +00:00
Jim Laskey
0e83541f8b Break out target asm info into separate files. 
llvm-svn: 30161
 2006-09-07 22:05:02 +00:00
Jim Laskey
a6211dcdad Separate target specific asm properties from the asm printers. 
llvm-svn: 30126
 2006-09-06 18:34:40 +00:00
Rafael Espindola
abd8bcbe5e add the orr instruction 
llvm-svn: 30125
 2006-09-06 18:03:12 +00:00
Chris Lattner
af23f9b5f6 Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.

llvm-svn: 30109
 2006-09-05 02:31:13 +00:00
Rafael Espindola
8386105f3f add support for returning 64bit values 
llvm-svn: 30103
 2006-09-04 19:05:01 +00:00
Chris Lattner
12e97307a1 Completely rearchitect the interface between targets and the pass manager. 
This pass:

1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
   output, move all this to common code, and give targets hooks they can
   implement.
3. Commonalize the target population stuff between file emission and JIT
   emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
   paves the way for "fast -O0" stuff in the CFE later, and now LLC could
   lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
   scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
   touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
   which is now orthogonal to the fact that JIT'ing is being done.

llvm-svn: 30081
 2006-09-04 04:14:57 +00:00
Chris Lattner
0fc4541c67 Simplify target construction. 
llvm-svn: 30070
 2006-09-03 18:44:02 +00:00
Rafael Espindola
5328ba96e1 add the SETULT condition code 
llvm-svn: 30067
 2006-09-03 13:19:16 +00:00
Rafael Espindola
c585b6919b add more condition codes 
llvm-svn: 30056
 2006-09-02 20:24:25 +00:00
Evan Cheng
61413a3d72 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Rafael Espindola
98dc23fd1f use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
 2006-08-25 17:55:16 +00:00
Rafael Espindola
29e4875f57 add the "eq" condition code 
implement a movcond instruction

llvm-svn: 29857
 2006-08-24 17:19:08 +00:00
Rafael Espindola
fe03fe9bf4 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola
e08b9853cc initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Rafael Espindola
ea500426d6 add a README.txt 
llvm-svn: 29814
 2006-08-22 12:22:46 +00:00
Rafael Espindola
d0dee77718 initial support for select 
llvm-svn: 29802
 2006-08-21 22:00:32 +00:00
Rafael Espindola
9d77f9fd24 add the and instruction 
llvm-svn: 29793
 2006-08-21 13:58:59 +00:00
Rafael Espindola
8a675a5d09 call computeRegisterProperties 
llvm-svn: 29780
 2006-08-20 01:49:49 +00:00
Chris Lattner
60f1eecd3a Constify some methods. Patch provided by Anton Vayvod, thanks! 
llvm-svn: 29756
 2006-08-17 22:00:08 +00:00
Rafael Espindola
c3ed77e1b9 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Rafael Espindola
bf8e751488 Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727
 2006-08-16 14:43:33 +00:00
Rafael Espindola
157971b04a select code like 
ldr rx, [ry, #offset]

llvm-svn: 29664
 2006-08-14 19:01:24 +00:00
Chris Lattner
ed728e8dc9 Eliminate use of getNode that takes a vector. 
llvm-svn: 29614
 2006-08-11 17:38:39 +00:00
Chris Lattner
c62914880f elimiante use of getNode that takes vector of operands. 
llvm-svn: 29612
 2006-08-11 17:22:35 +00:00
Evan Cheng
bd1c5a8fb8 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Evan Cheng
81b645a76b CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Rafael Espindola
1c41fc9b06 correctly set LocalAreaOffset of TargetFrameInfo 
llvm-svn: 29589
 2006-08-09 17:37:45 +00:00
Rafael Espindola
f5ce475540 fix the spill code 
llvm-svn: 29583
 2006-08-09 16:41:12 +00:00
Rafael Espindola
58159b36a3 fix the loading of the link register in emitepilogue 
llvm-svn: 29580
 2006-08-09 13:15:47 +00:00
Rafael Espindola
8c41f99e6f change the addressing mode of the str instruction to reg+imm 
llvm-svn: 29571
 2006-08-08 20:35:03 +00:00
Rafael Espindola
39083e7836 initial support for variable number of arguments 
llvm-svn: 29567
 2006-08-08 13:02:29 +00:00
Evan Cheng
b9d34bd098 Match tablegen isel changes. 
llvm-svn: 29549
 2006-08-07 22:28:20 +00:00
Rafael Espindola
2bcb8c0f05 use a 'register pressure reducing' scheduler 
make sure only one move is used in a hello world

llvm-svn: 29520
 2006-08-04 12:48:42 +00:00
Rafael Espindola
e19f6fde2d Bug fix: always generate a RET_FLAG in LowerRET 
fixes ret_null.ll and call.ll

llvm-svn: 29519
 2006-08-03 22:50:11 +00:00
Rafael Espindola
a94b9e33af add and use ARMISD::RET_FLAG 
llvm-svn: 29499
 2006-08-03 17:02:20 +00:00
Rafael Espindola
8b7bd8264b start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
 2006-08-01 18:53:10 +00:00
Rafael Espindola
95035cf001 implement LowerConstantPool and LowerGlobalAddress 
llvm-svn: 29433
 2006-08-01 12:58:43 +00:00