10 Commits

Author SHA1 Message Date
Craig Topper
fa42e7b6bc [RISCV] Merge RISCV::parseCPUKind and RISCV::checkCPUKind.
Similar for RISCV::parseTuneCPU and RISCV::checkTuneCPUKind.

This makes the CPUKind enum no longer part of the API. It wasn't
providing much value. It was only used to pass between the two
functions.

By removing it, we can remove a dependency on a tablegen generated
file from the RISCVTargetParser.h file. Then we can remove a
dependency from several CMakeLists.txt.
2023-05-01 13:00:05 -07:00
Paul Kirth
aa1d2693c2 [CodeGen][RISCV] Change Shadow Call Stack Register to X3
ShadowCallStack implementation uses s2 register on RISC-V, but that
choice is problematic for reasons described in:

https://lists.riscv.org/g/sig-toolchains/message/544,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370, and
https://github.com/google/android-riscv64/issues/72

The concern over the register choice was also brought up in
https://reviews.llvm.org/D84414.

https://reviews.llvm.org/D84414#2228666 said:

```
  "If the register choice is the only concern about this work, then I think
  we can probably land it as-is and fixup the register choice if we see
  major drawbacks later. Yes, it's an ABI issue, but on the other hand the
  shadow call stack is not a standard ABI anyway.""
```

Since we have now found a sufficient reason to fixup the register
choice, we should go ahead and update the implementation. We propose
using x3(gp) which is now the platform register in the RISC-V ABI.

Reviewed By: asb, hiraditya, mcgrathr, craig.topper

Differential Revision: https://reviews.llvm.org/D146463
2023-04-12 21:06:22 +00:00
Craig Topper
5e2d8a3528 [RISCV] Remove getCPUFeaturesExceptStdExt.
This function was used to force +64bit or -64bit into the feature
string basd on -mcpu.

It's not entirely clear to me why this was needed.  This informationo
is redundant with the triple. RISCVTargetInfo::initFeatureMap
independently recomputes it from the triple for the feature map.

It is ultimately needed in the backend, but that should be handled
by RISCVSubtarget processing the CPU name.

Differential Revision: https://reviews.llvm.org/D147978
2023-04-11 10:41:46 -07:00
Craig Topper
29463612d2 [RISCV] Replace RISCV -> RISC-V in comments. NFC
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449
2023-03-27 09:50:17 -07:00
AdityaK
9d0e5e79b0 [RISCV] Reserve X18 by default for Android
Reserve X18 even when -fsanitize=shadow-call-stack is not enabled.

Based on: https://reviews.llvm.org/D143355

Reviewed by: asb, samitolvanen, phosek, MaskRay

Differential Revision: https://reviews.llvm.org/D145999
2023-03-14 23:35:05 -07:00
Roland McGrath
03ff435da5 [RISCV] Default to -ffixed-x18 for Fuchsia
Fuchsia's ABI always reserves the x18 (s2) register for the
ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is
not enabled.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D143355
2023-02-05 18:51:18 -08:00
Craig Topper
0ccbf91166 [RISCV] Remove Features from CPUInfo in RISCVTargetParser.
Instead of having separate feature bits, get information from march.
Invalid is now implied by empty march.
64-bit is now implied by march starting with "rv64".

Reviewed By: fpetrogalli

Differential Revision: https://reviews.llvm.org/D142230
2023-01-20 10:03:37 -08:00
Francesco Petrogalli
ac1ffd3cac [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.
Rework the change to prevent build failures. NFCI.

The failing code was submitted as
cf7a8305a2b4ddfd299c748136cb9a2960ef7089 and reverted via
8bd65e535fb33bc48805bafed8217b16a853e158.

The rework in this new commit prevents failures like the following:

FAILED: tools/clang/lib/Basic/CMakeFiles/obj.clangBasic.dir/Targets/RISCV.cpp.o
/usr/bin/c++  [bunch of non interesting stuff]  -c <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
In file included from <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp:19:
<path-to>/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:29:10: fatal error: llvm/TargetParser/RISCVTargetParserDef.inc: No such file or directory
  29 | #include "llvm/TargetParser/RISCVTargetParserDef.inc"
     |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

These failures happen because the library LLVMTargetParser depends on
RISCVTargetParserTableGen, which is a tablegen target that generates
the list of CPUs in
llvm/TargetParser/RISCVTargetParserDef.inc. This *.inc file is
included by the public header file
llvm/TargetParser/RISCVTargetParser.h.

The header file llvm/TargetParser/RISCVTargetParser.h is also used in
components (clangDriver and clangBasic) that link into
LLVMTargetParser, but on some configurations such components might end
up being built before TargetParser is ready.

The fix is to make sure that clangDriver and clangBasic depend on the
tablegen target RISCVTargetParserTableGen, which generates the .inc
file whether or not LLVMTargetParser is ready.

WRT the original patch at https://reviews.llvm.org/D137517, this
commit is just adding RISCVTargetParserTableGen in the DEPENDS list of
clangDriver and clangBasic.
2023-01-11 11:18:44 +01:00
Francesco Petrogalli
8bd65e535f Revert "[TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen."
This reverts commit cf7a8305a2b4ddfd299c748136cb9a2960ef7089.
2023-01-11 10:22:56 +01:00
Francesco Petrogalli
cf7a8305a2 [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.
This patch removes the file `llvm/include/llvm/TargetParser/RISCVTargetParser.def` and replaces it with a tablegen-generated `.inc` file out of `llvm/lib/Target/RISCV/RISCV.td`.

The module system has been updated to make sure we can build clang/llvm with `-DLLVM_ENABLE_MODULES=On`

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D137517
2023-01-11 10:00:04 +01:00