683 Commits

Author SHA1 Message Date
Jeffrey Byrnes
66b481556e
[AMDGPU][AsmParser]: Use dummy operand for parsing buffer_ SWZ operand. (#165305)
`MCInstrDesc` counts the SWZ operand for `NumOperands` -- thus, since we
do not parse this into the `MCInst` operands, there will be a mismatch
between `MCInst.getNumOperands` and `MCInstrDesc.getNumOperands` .

`llvm-mca` assumes that each operand counted by
`MCInstrDesc.getNumOperands` will be present in `MCInst.operands`
263377a175/llvm/lib/MCA/InstrBuilder.cpp (L324)

This parses a dummy operand for the buffer_loads as a placeholder for
the implicit SWZ operand. This is similar to the parsing of `tbuffer_`
variants which automatically parse the dummy operand
263377a175/llvm/utils/TableGen/AsmMatcherEmitter.cpp (L1853)
2025-10-27 18:39:59 -07:00
Stanislav Mekhanoshin
997af95fac
[AMDGPU] Remove validation of s_set_vgpr_msb range (#164888)
We will need the full 16-bit range of the operand to record
previous mode.
2025-10-23 15:45:35 -07:00
Ivan Kosarev
3d4da1ee81
[AMDGPU][MC] Do not inline lit()/lit64() operands. (#162137)
For now treat the modifiers synonymous to each other.

The disassembler side is to be addressed separately.
2025-10-08 12:43:42 +01:00
Ivan Kosarev
20f41ed8c1
[AMDGPU][MC] Avoid creating lit64() operands unless asked or needed. (#161191)
There should normally be no need to generate implicit lit64()
modifiers on the assembler side. It's the encoder's responsibility
to recognise literals that are implicitly 64 bits wide.

The exceptions are where we rewrite floating-point operand values
as integer ones, which would not be assembled back to the original
values unless wrapped into lit64().

Respect explicit lit() modifiers for non-inline values as
necessary to avoid regressions in MC tests. This change still
doesn't prevent use of inline constants where lit()/lit64 is
specified; subject to a separate patch.

On disassembling, only create lit64() operands where necessary for
correct round-tripping.

Add round-tripping tests where useful and feasible.
2025-10-08 10:51:55 +01:00
Matt Arsenault
1a5494ca4a
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
This removes special case processing in TargetInstrInfo::getRegClass to
fixup register operands which depending on the subtarget support AGPRs,
or require even aligned registers.

This regresses assembler diagnostics, which currently work by hackily
accepting invalid cases and then post-rejecting a validly parsed
instruction.
On the plus side this now emits a comment when disassembling unaligned
registers for targets with the alignment requirement.
2025-10-08 11:19:54 +09:00
Jun Wang
64190462f7
[AMDGPU][MC] GFX9 - allow op_sel in v_interp_p2_f16 (#150712)
AMDGPU documentation states op_sel[3] can be used in v_interp_p2_f16 in
GFX9.
2025-10-06 10:58:13 -07:00
Rahul Joshi
2a72522c52
[NFC][LLVM] Pass/return SMLoc by value instead of const reference (#160797)
SMLoc itself encapsulates just a pointer, so there is no need to pass or
return it by reference.
2025-09-26 08:58:35 -07:00
Matt Arsenault
0a80631142
AMDGPU: Ensure both wavesize features are not set (#159234)
Make sure we cannot be in a mode with both wavesizes. This
prevents assertions in a future change. This should probably
just be an error, but we do not have a good way to report
errors from the MCSubtargetInfo constructor.
2025-09-25 09:46:34 +00:00
Ivan Kosarev
9e55d81c68
[AMDGPU][AsmParser] Introduce MC representation for lit() and lit64(). (#160316)
And rework the lit64() support to use it.

The rules for when to add lit64() can be simplified and
improved. In this change, however, we just follow the existing
conventions on the assembler and disassembler sides.

In codegen we do not (and normally should not need to) add explicit
lit() and lit64() modifiers, so the codegen tests lose them. The change
is an NFCI otherwise.

Simplifies printing operands.
2025-09-24 12:35:50 +01:00
Ivan Kosarev
f3762b7b71
[AMDGPU][AsmParser][NFC] Combine the Lit and Lit64 modifier flags. (#160315)
They represent mutually exclusive values of the same attribute.
2025-09-23 17:49:18 +01:00
Matt Arsenault
7dc7d0e129
AMDGPU: Remove subtarget feature hacking in AsmParser (#159227)
The wavesize hacking part was already done in
createAMDGPUMCSubtargetInfo, and we can move the default
target hack there too.
2025-09-17 12:09:53 +09:00
Ivan Kosarev
7ba7021951
[AMDGPU][MC] Keep MCOperands unencoded. (#158685)
We have proper encoding facilities to encode operands and instructions;
there's no need to pollute the MC representation with encoding details.

Supposed to be an NFCI, but happens to fix some re-encoded instruction
codes in disassembler tests.

The 64-bit operands are to be addressed in following patches introducing
MC-level representation for lit() and lit64() modifiers, to then be
respected by both the assembler and disassembler.
2025-09-16 09:01:01 +01:00
Ivan Kosarev
ed165237cd
[AMDGPU][AsmParser] Simplify getting source locations of operands. (#158323)
Remember indexes of MCOperands in MCParsedAsmOperands as we add them to
instructions. Then use the indexes to find locations by known MCOperands
indexes.

Happens to fix some reported locations in tests. NFCI otherwise.

getImmLoc() is to be eliminated as well; there's enough work for another
patch.
2025-09-15 17:13:31 +01:00
Pierre van Houtryve
dcaa29c8ed
Revert "[AMDGPU][gfx1250] Add cu-store subtarget feature (#150588)" (#157639)
This reverts commit be17791f2624f22b3ed24a2539406164a379125d.

This is not necessary for gfx1250 anymore.
2025-09-10 10:20:59 +02:00
Matt Arsenault
811538eb50
AMDGPU: Check aligned vgpr feature in assembler (#156997)
Use the new feature instead of listing the two separate cases.
2025-09-06 08:28:35 +09:00
Aleksandar Spasojevic
1b47135c9d
[AMDGPU] Ensure positive InstOffset for buffer operations (#145504)
GFX12+ buffer ops require positive InstOffset per AMD hardware spec.
Modified assembler/disassembler to reject negative buffer offsets.
2025-09-04 15:37:46 +02:00
Jay Foad
837a706fb6
[AMDGPU] Fix source location for assembler warnings (#156621)
Call MCInst::setLoc earlier so it is available for warnings generated
during MatchInstructionImpl.
2025-09-04 10:43:47 +01:00
Stanislav Mekhanoshin
6aebbb0a85
[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)
This is a baseline support, it is not useable yet.
2025-09-03 16:25:18 -07:00
Stanislav Mekhanoshin
cc9acb9df7
[AMDGPU] Add s_set_vgpr_msb gfx1250 instruction (#156524) 2025-09-02 14:22:57 -07:00
Jeremy Kun
be2f0205b6
NFC: remove some instances of deprecated capture (#154884)
```
 warning: implicit capture of 'this' with a capture default of '=' is deprecated [-Wdeprecated-this-capture]
```

Co-authored-by: Jeremy Kun <j2kun@users.noreply.github.com>
2025-08-26 20:29:26 +00:00
Stanislav Mekhanoshin
438c099c23
[AMDGPU] gfx1250 kernel descriptor update (#155008) 2025-08-22 12:58:41 -07:00
Gang Chen
60dbde69cd
[AMDGPU] report named barrier cnt part2 (#154588) 2025-08-20 12:00:45 -07:00
Stanislav Mekhanoshin
57c1e01e48
[AMDGPU] Don't allow wgp mode on gfx1250 (#153680)
- gfx1250 only supports cu mode
2025-08-14 15:16:56 -07:00
Stanislav Mekhanoshin
ea14834966
[AMDGPU] Per-subtarget DPP instruction classification (#153096)
This is NFCI at this point.
2025-08-11 15:41:02 -07:00
Stanislav Mekhanoshin
dddeb07c2e
[AMDGPU] Restrict packed math FP32 instructions to read only one SGPR per operand on gfx12+ (#152465)
Sec. 4.6.7.1 of the gfx1250 SPG states that if an SGPR is used
as an operand, only one SGPR will be read for both the low and high
operations. As a result, the corresponding bits in `op_sel` and
`op_sel_hi` must be the same when the operand is an SGPR.

Co-authored-by: Tian, Shilei <Shilei.Tian@amd.com>

Co-authored-by: Tian, Shilei <Shilei.Tian@amd.com>
2025-08-07 16:13:34 -07:00
Stanislav Mekhanoshin
d08c2977e8
[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203) 2025-08-05 14:35:48 -07:00
Stanislav Mekhanoshin
dd0737bd99
[AMDGPU] gfx1250 v_wmma_ld_scale instructions (#152010) 2025-08-04 11:36:48 -07:00
Stanislav Mekhanoshin
c7bb105e97
[AMDGPU] Add v_cvt_scale_pk8_* gfx1250 instructions (#151616) 2025-07-31 18:55:59 -07:00
Stanislav Mekhanoshin
49d89bc9f4
[AMDGPU] Add gfx1250 cvt_pk|sr_fp8|bf8_f32 instructions (#151595) 2025-07-31 16:04:46 -07:00
Stanislav Mekhanoshin
ce40863209
[AMDGPU] Add v_cvt_sr|pk_bf8|fp8_f16 gfx1250 instructions (#151415) 2025-07-30 17:24:45 -07:00
Pierre van Houtryve
be17791f26
[AMDGPU][gfx1250] Add cu-store subtarget feature (#150588)
Determines whether we can use `SCOPE_CU` stores (on by default), or
whether all stores must be done at `SCOPE_SE` minimum.
2025-07-29 11:38:43 +02:00
Stanislav Mekhanoshin
a0b854d576
[AMDGPU] MC support for gfx1250 scale_offset modifier (#149881) 2025-07-21 15:04:59 -07:00
Stanislav Mekhanoshin
b66084acd9
[AMDGPU] Verify asm VGPR alignment on gfx1250 (#149880)
Co-authored-by: Shilei Tian <Shilei.Tian@amd.com>
2025-07-21 14:23:27 -07:00
Changpeng Fang
d6094370cb
AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
2025-07-21 10:09:42 -07:00
Stanislav Mekhanoshin
6d8e53d4af
[AMDGPU] Support nv memory instructions modifier on gfx1250 (#149582) 2025-07-18 14:38:46 -07:00
Kazu Hirata
ff5f355d9b
[AMDGPU] Use a range-based for loop (NFC) (#148767) 2025-07-15 08:02:46 -07:00
Changpeng Fang
b80b02536b
AMDGPU: Implement MC layer support for gfx1250 wmma instructions. (#148570)
Regular wmma/swmmac plus matrix reuse only.

---------

Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Co-authored-by: Shilei Tian <Shilei.Tian@amd.com>
2025-07-15 00:48:57 -07:00
Stanislav Mekhanoshin
f090554359
[AMDGPU] MC support for v_fmaak_f64/v_fmamk_f64 gfx1250 intructions (#148282) 2025-07-11 14:17:03 -07:00
Stanislav Mekhanoshin
7920dff394
[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602) 2025-07-10 14:15:01 -07:00
Stanislav Mekhanoshin
00a85e5704
[AMDGPU] gfx1250: MC support for 64-bit literals (#147861) 2025-07-09 22:25:47 -07:00
Shilei Tian
d258457d42
[AMDGPU] Add support for v_cvt_f32_fp8 on gfx1250 (#147579)
Co-authored-by: Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>
2025-07-08 16:21:24 -04:00
Changpeng Fang
eda3161c35
AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
2025-07-03 13:49:34 -07:00
Fangrui Song
e878b7e349 MCParsedAsmOperand::print: Add MCAsmInfo parameter
so that subclasses can provide the appropriate MCAsmInfo to print
MCExpr objects.

At present, llvm/utils/TableGen/AsmMatcherEmitter.cpp constucts a
generic MCAsmInfo.
2025-06-28 12:05:33 -07:00
Fangrui Song
d93aff42c2 MC: Migrate away from operator<< MCExpr
MCExpr::print has an optional MCAsmInfo argument, which is error-prone
when omitted. MCExpr::print and the convenience helper operator<< are
discouraged to use. Switch to MCAsmInfo::printExpr instead. Use the
target-specific MCAsmInfo if available.
2025-06-28 10:58:09 -07:00
Kazu Hirata
eff28bdd46
[AMDGPU] Use StringRef::consume_back (NFC) (#146194)
Note that StringRef::consume_back returns true while consuming the
given prefix if present.
2025-06-27 22:07:27 -07:00
Andrew Rogers
19658d1474
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
## Purpose

This patch is one in a series of code-mods that annotate LLVM’s public
interface for export. This patch annotates the `llvm/Target` library.
These annotations currently have no meaningful impact on the LLVM build;
however, they are a prerequisite to support an LLVM Windows DLL (shared
library) build.

## Background

This effort is tracked in #109483. Additional context is provided in
[this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).

A sub-set of these changes were generated automatically using the
[Interface Definition Scanner (IDS)](https://github.com/compnerd/ids)
tool, followed formatting with `git clang-format`.

The bulk of this change is manual additions of `LLVM_ABI` to
`LLVMInitializeX` functions defined in .cpp files under llvm/lib/Target.
Adding `LLVM_ABI` to the function implementation is required here
because they do not `#include "llvm/Support/TargetSelect.h"`, which
contains the declarations for this functions and was already updated
with `LLVM_ABI` in a previous patch. I considered patching these files
with `#include "llvm/Support/TargetSelect.h"` instead, but since
TargetSelect.h is a large file with a bunch of preprocessor x-macro
stuff in it I was concerned it would unnecessarily impact compile times.

In addition, a number of unit tests under llvm/unittests/Target required
additional dependencies to make them build correctly against the LLVM
DLL on Windows using MSVC.

## Validation

Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:

- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
2025-06-17 13:28:45 -07:00
Shilei Tian
9a237f35ef
[AMDGPU][AsmParser] Support true16 register suffix for valid register range (#143997) 2025-06-13 08:39:00 -04:00
Brox Chen
d2f06b2729
[AMDGPU][True16][MC][CodeGen] true16 mode for v_cvt_pk_bf8/fp8_f32 (#141881)
Update true16/fake16 profile with v_cvt_pk_bf8/fp8_f32, keeping the
vdst_in profile, and update codegen pattern.

update mc test and codegen test.
2025-06-04 11:29:26 -04:00
Vigneshwar Jayakumar
b3a8c1ef3a
[AMDGPU] Bugfix for scaled MFMA parsing FP literals (#142493)
bugfix on parsing FP literals for scale values in the scaled MFMA.

Due to the change in order of operands between MCinst and parsed
operands, the FP literal imms for scale values were not parsed
correctly.

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2025-06-03 19:27:57 -05:00
Fangrui Song
b3873e8aa4 MCSymbol: Remove the default argument of getVariableValue
It has been made ineffective by e015626f189dc76f8df9fdc25a47638c6a2f3feb.
This change migrates the users.
2025-05-27 20:34:18 -07:00