33333 Commits

Author SHA1 Message Date
Ramkumar Ramachandra
1de55c9693
[VPlan] Avoid sinking allocas in sinkScalarOperands (#166135)
Use cannotHoistOrSinkRecipe to forbid sinking allocas.
2025-11-05 13:06:24 +00:00
David Sherwood
7b3fe5fd42
[LV][NFC] Remove undef values in some test cases (#164401)
Split off from PR #163525, this standalone patch replaces simple cases
where undef is used as a value for arithmetic or getelementptr
instructions. This will reduce the likelihood of contributors hitting
the `undef deprecator` warning in github.
2025-11-05 09:18:02 +00:00
Gábor Spaits
628d53aba5
[InstCombine] Enable FoldOpIntoSelect and foldOpIntoPhi when the Op's other parameter is non-const (#166102)
This patch enables `FoldOpIntoSelect` and `foldOpIntoPhi` for the cases
when Op's second parameter is a non-constant.
It doesn't seem to bring significant improvements, but the compile
time impact is neglegable.
2025-11-05 10:04:32 +01:00
Mircea Trofin
1458d313a1
[SLU][profcheck] Propagate profile for branches on injected conditions. (#164476)
This patch addresses the profile of 2 branches:

- one that compares the 2 limits, for which we have no information (the C1, C2, see https://reviews.llvm.org/D136233)
- one that is conditioned on a condition for which we have a profile, so we reuse it



Issue #147390
2025-11-04 17:23:55 -08:00
Mircea Trofin
d547931137
[SLU][profcheck] create likely branch weights for guard->branch (#164271)
The `llvm.experimental.guard` intrinsic is a `call`, so its metadata - if present - would be one value (as per `Verifier::visitProfMetadata`). That wouldn't be a correct `branch_weights` metadata. Likely, `GI->getMetadata(LLVMContext::MD_prof)` was always `nullptr`.

We can bias away from deopt instead.

Issue #147390
2025-11-04 16:39:12 -08:00
Jin Huang
fa5cd27ef0
[profcheck] Add unknown branch weights to expand LL/SR loop. (#166273)
As a follow-up to PR#165841, this change addresses `prof_md` metadata
loss in AtomicExpandPass when lowering `atomicrmw xchg` to a
Load-Linked/Store-Exclusive (LL/SC) loop.

This path is distinct from the LSE path addressed previously:

PR #165841 (and its tests) used `-mtriple=aarch64-linux-gnu`, which
targets a modern **ARMv8.1+** architecture. This architecture supports
**Large System Extensions (LSE)**, allowing `atomicrmw` to be lowered
directly to a more efficient hardware instruction.

This PR (and its tests) uses `-mtriple=aarch64--` or
`-mtriple=armv8-linux-gnueabihf`. This indicates an `ARMv8.0 or lower
architecture that does not support LSE`. On these targets, the pass must
fall back to synthesizing a manual LL/SC loop using the `ldaxr/stxr`
instruction pair.

Similar to previous issue, the new conditional branch was failin to
inherit the `prof_md` metadata. Theis PR correctly fix the branch
weights to the newly created branch within the LL/SC loop, ensuring
profile information is preserved.

Co-authored-by: Jin Huang <jingold@google.com>
2025-11-04 16:23:34 -08:00
Alireza Torabian
025e431e74
[LoopFusion] Forget loop and block dispositions after latch merge (#166233)
Merging the latches of loops may affect the dispositions, so they should
be forgotten after the merge. This patch fixed the crash in loop fusion
[#164082](https://github.com/llvm/llvm-project/issues/164082).
2025-11-04 16:48:39 -05:00
Matt Arsenault
e5f191e171 DeclareRuntimeLibcalls: Add registered target checks to test run lines 2025-11-04 11:23:02 -08:00
Mircea Trofin
2bc22ea02e
[NFC][SLU] Update SimpleLoopUnswitch/guards.ll (#166285)
When running UTC on SLU/guards.ll (without LLVM changes), there are a number of changes in the UTC-generated checks. Submitting those first to simplify the diff of PR #164271, as most of the changes in the latter were actually these.
2025-11-04 11:00:35 -08:00
Matt Arsenault
fb21f16fe6
RuntimeLibcalls: Add stub API for getting function signatures (#166290)
Eventually this should be generated by tablegen for all functions.
For now add a manually implementation for sincos_stret, which I
have an immediate use for. This will allow pulling repeated code
across targets into shared call sequence code.

Also add sqrt just to make sure we can handle adding return attributes
on the declaration.
2025-11-04 10:06:29 -08:00
Joel E. Denny
1aa86ca521
[LoopUnroll] Fix division by zero (#166258)
PR #159163's probability computation for epilogue loops does not handle
the possibility of an original loop probability of one. Runtime loop
unrolling does not make sense for such an infinite loop, and a division
by zero results. This patch works around that case.

Issue #165998.
2025-11-04 12:49:33 -05:00
Yingwei Zheng
4ce58833d3
[SimplifyCFG] Fix value enumeration of a full range (#166379)
ConstantRange uses `[-1, -1)` as the canonical form of a full set.
Therefore, the `for (APInt I = Lower; I != Upper; ++I)` idiom doesn't
work for full ranges. This patch fixes the value enumeration in
`ConstantComparesGatherer` to prevent missing values for full sets.

Closes https://github.com/llvm/llvm-project/issues/166369.
2025-11-05 01:43:05 +08:00
Ivan Kelarev
37825ad4f6
[LoopUnroll] Prevent LoopFullUnrollPass from performing partial unrolling when trip counts are unknown (#165013)
Currently, `LoopFullUnrollPass` incorrectly performs partial unrolling
when `#pragma unroll` is specified and both `TripCount` and
`MaxTripCount` are unknown. This patch adds a check to prevent partial
unrolling when `OnlyFullUnroll` parameter is true and both trip count
values are zero.
2025-11-04 09:20:01 -08:00
Florian Hahn
af9a4263a1
[LAA] Only use inbounds/nusw in isNoWrap if the GEP is dereferenced. (#161445)
Update isNoWrap to only use the inbounds/nusw flags from GEPs that are
guaranteed to be dereferenced on every iteration. This fixes a case
where we incorrectly determine no dependence.

I think the issue is isolated to code that evaluates the resulting
AddRec at BTC, just using it to compute the distance between accesses
should still be fine; if the access does not execute in a given
iteration, there's no dependence in that iteration. But isolating the
code is not straight-forward, so be conservative for now. The practical
impact should be very minor (only one loop changed across a corpus with
27k modules from large C/C++ workloads.

Fixes https://github.com/llvm/llvm-project/issues/160912.

PR: https://github.com/llvm/llvm-project/pull/161445
2025-11-04 17:08:12 +00:00
Yingwei Zheng
8a84b285f6
[SimplifyCFG] Eliminate dead edges of switches according to the domain of conditions (#165748)
In simplifycfg/cvp/sccp, we eliminate dead edges of switches according
to the knownbits/range info of conditions. However, these approximations
may not meet the real-world needs when the domain of condition values is
sparse. For example, if the condition can only be either -3 or 3, we
cannot prove that the condition never evaluates to 1 (knownbits:
???????1, range: [-3, 4)).
This patch adds a helper function `collectPossibleValues` to enumerate
all the possible values of V. To fix the motivating issue,
`eliminateDeadSwitchCases` will use the result to remove dead edges.

Note: In
https://discourse.llvm.org/t/missed-optimization-due-to-overflow-check/88700
I proposed a new value lattice kind to represent such values. But I find
it hard to apply because the transition becomes much complicated.

Compile-time impact looks neutral:
https://llvm-compile-time-tracker.com/compare.php?from=32d6b2139a6c8f79e074e8c6cfe0cc9e79c4c0c8&to=e47c26e3f1bf9eb062684dda4fafce58438e994b&stat=instructions:u
This patch removes many dead error-handling codes:
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/3012
Closes https://github.com/llvm/llvm-project/issues/165179.
2025-11-04 20:55:33 +08:00
Julian Nagele
28a20b4af9
[VectorCombine] Avoid inserting freeze when scalarizing extend-extract if all extracts would lead to UB on poison. (#164683)
This change aims to avoid inserting a freeze instruction between the
load and bitcast when scalarizing extend-extract. This is particularly
useful in combination with
https://github.com/llvm/llvm-project/pull/164682, which can then
potentially further scalarize, provided there is no freeze.

alive2 proof: https://alive2.llvm.org/ce/z/W-GD88
2025-11-04 12:39:04 +00:00
Jay Foad
f037f41350
[IR] Add new function attribute nocreateundeforpoison (#164809)
Also add a corresponding intrinsic property that can be used to mark
intrinsics that do not introduce poison, for example simple arithmetic
intrinsics that propagate poison just like a simple arithmetic
instruction.

As a smoke test this patch adds the new property to
llvm.amdgcn.fmul.legacy.
2025-11-04 12:00:44 +00:00
kper
5b2f9b53bd
[SimplifyCFG]: Switch on umin replaces default (#164097)
A switch on `umin` can eliminate the default case by making the `umin`'s
constant the default case.

Proof: https://alive2.llvm.org/ce/z/_N6nfs
Fixes: https://github.com/llvm/llvm-project/issues/162111
2025-11-04 18:35:40 +08:00
David Green
6ad25c5912
[AArch64] Improve the cost model for extending mull (#125651)
We already have cost model code for detecting extending mull multiplies
for the form `mul(ext, ext)`. Since it was added the codegen for mull
has been improved, this attempts to catch the cost model up.

The main idea is to incorporate extends of larger sizes. A vector `v8i32
mul(zext(v8i8), zext(v8i8))` will be code-generated as `zext (v8i16
mul(zext(v8i8), zext(v8i8))`, or umull+ushll+ushll2.

So the total cost should be 3ish if each instruction costs 1. Where
exactly we attribute the costs is dependable, this patch opts to sets
the cost of the extend to 0 (or the cost of the extend not included in
the mull) and the mul gets the cost of the mull+extra extends.

isWideningInstruction is split into two functions for the two types of
operands it supports. isSingleExtWideningInstruction now handles addw
instructions that extend the second operand, isBinExtWideningInstruction
is for instructions like addl that extend both operands.
2025-11-04 07:50:51 +00:00
Shoreshen
00ee53cc7b
[Attributor] Propagate alignment through ptrmask (#150158)
Propagate alignment through ptrmask based on potential constant values
of mask and align of ptr.

---------

Co-authored-by: Shilei Tian <i@tianshilei.me>
2025-11-04 12:26:17 +08:00
choikwa
2b45efe920
[AMDGPU] NFC, move testcase, only test output of promote-alloca with vector-combine (#166289) 2025-11-03 22:21:26 -05:00
Mircea Trofin
01221874e4
[SLU][profcheck] Use the original branch weigths in buildPartialInvariantUnswitchConditionalBranch (#164270)
A new branch is created on the same condition as a branch for which we have a profile. We can reuse that profile in this case.

Issue #147390
2025-11-03 14:37:41 -08:00
Robert Imschweiler
a8ea7f4580
Reapply: [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161) (#166195)
Reapply #152161 with fixed 'changed' flags.
2025-11-03 20:59:48 +01:00
Alan Zhao
c4763e2b90
[profcheck][InstCombine] Preserve branch weights in logical identities (#165810)
For the simplification
```
(C && A) || (!C && B) --> sel C, A, B
```
(and related), if `C` (or (`!C`)) is the condition in the select
instruction representing the logical and, we can preserve that logical
and's branch weights when emitting the new instruction. Otherwise, the
profile data is unknown.

If `C` is the condition of both logical ands, then we just take the
branch weights of the first logical and (though in practice they should
be equal.)

Furthermore, `select-safe-transforms.ii` now passes under the profcheck
configuration, so we remove it from the failing tests.

Tracking issue: #147390
2025-11-03 09:32:42 -08:00
Robert Imschweiler
af68efc9c4
Revert "[AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm" (#166186)
Reverts llvm/llvm-project#152161

Need to revert to fix changed logic for the expensive checks.
2025-11-03 16:33:20 +00:00
Alexey Bataev
7d5659083c [SLP]Do not create copyable node, if parent node is non-schedulable and has a use in binop.
If the parent node is non-schedulable (only externally used instructions), and at least one instruction has multiple uses and used in the binop, such copyable node should be created. Otherwise, it may contain wrong def-use chain model, which cannot be effective detected.

Fixes #166035
2025-11-03 08:00:22 -08:00
Joel E. Denny
bb9bd5f263
[LoopUnroll] Fix assert fail on zeroed branch weights (#165938)
BranchProbability fails an assert when its denominator is zero.

Reported at
<https://github.com/llvm/llvm-project/pull/159163#pullrequestreview-3406318423>.
2025-11-03 10:19:12 -05:00
Robert Imschweiler
332f9b5eee
[AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (#152161)
Finishes adding inline-asm callbr support for AMDGPU, started by
https://github.com/llvm/llvm-project/pull/149308.
2025-11-03 16:09:12 +01:00
Luke Lau
e17bc1ec51
[VPlan] Explicitly predicate some replicate region sinking tests. NFC (#164934)
To remove some test diffs in #160449
2025-11-03 12:19:50 +00:00
Hassnaa Hamdi
8998df2097
[DropUnnecessaryAssumes] Don't drop public_type_test intrinsic (#166034)
Don't drop `assume` intrinsic when it's using `public_type_test `
intrinsic, as it could be used by devirtualization.
2025-11-03 10:34:44 +00:00
Sander de Smalen
f17c95ba54 [LV] Simplify vplan-printing.ll test (NFC)
This simplifies the test by moving some of the complicated options
to loop attributes, so that it's easier to extend the test file
with new cases.

The options `-enable-epilogue-vectorization` and
`-epilogue-vectorization-force-VF=2` were not strictly necessary
for the test.
2025-11-03 08:34:23 +00:00
Wenju He
79bf8c0331
[InstCombine] Fold select(X >s 0, 0, -X) | smax(X, 0) to abs(X) (#165200)
The IR pattern is compiled from OpenCL code:
  __builtin_astype(x > (uchar2)(0) ? x : -x, uchar2);
where smax is created by foldSelectInstWithICmp + canonicalizeSPF.

smax could also come from direct elementwise max call:
  int c = b > (int)(0) ? (int)(0) : -b;
  int d = __builtin_elementwise_max(b, (int)(0));
  *a = c | d;

https://alive2.llvm.org/ce/z/2-brvr
https://alive2.llvm.org/ce/z/Dowjzk
https://alive2.llvm.org/ce/z/kathwZ

---------

Co-authored-by: Yingwei Zheng <dtcxzyw@qq.com>
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2025-11-03 07:38:21 +08:00
Florian Hahn
b0fc9650f7 [LV] Add tests with hoist-able invariant loads. 2025-11-02 16:10:45 +00:00
Florian Hahn
d3fe1df194
[SCEV] Improve handling of divisibility information from loop guards. (#163021)
At the moment, the effectivness of guards that contain divisibility
information (A % B == 0 ) depends on the order of the conditions.

This patch makes using divisibility information independent of the
order, by collecting and applying the divisibility information
separately.

We first collect all conditions in a vector, then collect the
divisibility information from all guards.

When processing other guards, we apply divisibility info collected
earlier.

After all guards have been processed, we add the divisibility info,
rewriting the existing rewrite. This ensures we apply the divisibility
info to the largest rewrite expression.

This helps to improve results in a few cases, one in
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2921 and another one
in a different large C/C++ based IR corpus.

PR: https://github.com/llvm/llvm-project/pull/163021
2025-11-02 14:16:24 +00:00
Florian Hahn
b7e922a3da
[VPlan] Convert BuildVector with all-equal values to Broadcast. (#165826)
Fold BuildVector where all operands are equal to Broadcast of the first
operand. This will subsequently make it easier to remove additional
buildvectors/broadcasts, e.g. via
https://github.com/llvm/llvm-project/pull/165506.

PR: https://github.com/llvm/llvm-project/pull/165826
2025-11-01 17:28:42 -07:00
Florian Hahn
90bbffec02
[VPlan] Add VPlan printing tests for recipes with metadata. 2025-11-01 22:05:51 +00:00
Alexey Bataev
66b69d518a [SLP][NFC]Fix UB and constant folded ops in test, NFC 2025-11-01 11:50:39 -07:00
azwolski
7631c73850
[InstCombine] Baseline test exposing vector fp-to-int conversion becoming scalar (#165800)
Baseline test for https://github.com/llvm/llvm-project/issues/165793
exposing the change from a vector fp-to-int conversion into a scalar one
inside the loop.

Additionally, removed
`llvm/test/Transforms/InstCombine/vec_extract_var_elt-inseltpoison.ll`,
which was a duplicate of
`llvm/test/Transforms/InstCombine/vec_extract_var_elt.ll` differing only
by the use of poison in the insert element.
The poison variant has been merged into
`llvm/test/Transforms/InstCombine/vec_extract_var_elt.ll`.

Also improved test naming and updated test checks.
2025-11-01 15:25:50 +08:00
Mircea Trofin
6adef40e75
[SimplifyCFG] Don't propagate weights to unconditional branches in turnSwitchRangeIntoICmp (#165931)
PR #161000 introduced a bug whereby the IR would become invalid by having an unconditional branch have `!prof`​attached to it. This only became evident in PR #165744, because the IR of `test/Transforms/SimplifyCFG/pr165301.ll`​was simple enough to both (1) introduce the unconditional branch, and (2) survive in that fashion until the end of the pass (simplifycfg) and thus trip the verifier.
2025-10-31 23:10:59 +00:00
Alexey Bataev
964c7711f4 [SLP]Fix the minbitwidth analysis for slternate opcodes
If the laternate operation is more stricter than the main operation, we
cannot rely on the analysis of the main operation. In such case, better
to avoid doing the analysis at all, since it may affect the overall
result and lead to incorrect optimization

Fixes #165878
2025-10-31 15:25:13 -07:00
Alexey Bataev
4ac74fc614 [SLP][NFC]Add a test with the incorrect minbitwidth in alternate nodes, NFC 2025-10-31 14:52:19 -07:00
Aiden Grossman
c528f60573 Revert "[SLP][NFC]Add a test with the incorrect minbitwidth in alternate nodes, NFC"
This reverts commit 0dca7ee4480f11cd0230d316ccc5d2c7234a4b31.

This broke check-llvm, including on premerge.

https://lab.llvm.org/buildbot/#/builders/137/builds/28194
https://lab.llvm.org/staging/#/builders/21/builds/7649
2025-10-31 21:02:55 +00:00
Alexey Bataev
0dca7ee448 [SLP][NFC]Add a test with the incorrect minbitwidth in alternate nodes, NFC 2025-10-31 13:19:02 -07:00
Mircea Trofin
fe8ab75b40
[SimplifyCFG] Propagate profile in simplifySwitchOfPowersOfTwo (#165804)
`simplifySwitchOfPowersOfTwo`​ converts (when applicable, see `00f5a1e30b`​) a switch to a conditional branch. Its false case goes to the `default`​ target of the former switch, and the true case goes to a BB performing a `cttz`​. We can calculate the branch weights from the branch weights of the old switch.

Issue #147390
2025-10-31 13:05:18 -07:00
Joel E. Denny
cc8ff73fba
[LoopUnroll] Fix block frequencies for epilogue (#159163)
As another step in issue #135812, this patch fixes block frequencies for
partial loop unrolling with an epilogue remainder loop. It does not
fully handle the case when the epilogue loop itself is unrolled. That
will be handled in the next patch.

For the guard and latch of each of the unrolled loop and epilogue loop,
this patch sets branch weights derived directly from the original loop
latch branch weights. The total frequency of the original loop body,
summed across all its occurrences in the unrolled loop and epilogue
loop, is the same as in the original loop. This patch also sets
`llvm.loop.estimated_trip_count` for the epilogue loop instead of
relying on the epilogue's latch branch weights to imply it.

This patch fixes branch weights in tests that PR #157754 adversely
affected.
2025-10-31 11:01:42 -04:00
Joel E. Denny
24557cce40
[LoopUnroll] Fix block frequencies when no runtime (#157754)
This patch implements the LoopUnroll changes discussed in [[RFC] Fix
Loop Transformations to Preserve Block

Frequencies](https://discourse.llvm.org/t/rfc-fix-loop-transformations-to-preserve-block-frequencies/85785)
and is thus another step in addressing issue #135812.

In summary, for the case of partial loop unrolling without a remainder
loop, this patch changes LoopUnroll to:

- Maintain branch weights consistently with the original loop for the
sake of preserving the total frequency of the original loop body.
- Store the new estimated trip count in the
`llvm.loop.estimated_trip_count` metadata, introduced by PR #148758.
- Correct the new estimated trip count (e.g., 3 instead of 2) when the
original estimated trip count (e.g., 10) divided by the unroll count
(e.g., 4) leaves a remainder (e.g., 2).

There are loop unrolling cases this patch does not fully fix, such as
partial unrolling with a remainder loop and complete unrolling, and
there are two associated tests whose branch weights this patch adversely
affects. They will be addressed in future patches that should land with
this patch.
2025-10-31 10:44:27 -04:00
Teresa Johnson
c8e2f43379
[MemProf] Select largest of matching contexts from profile (#165338)
We aren't currently deduplicating contexts that are identical or nearly
identical (differing inline frame information) when generating the
profile. When we have multiple identical contexts we end up
conservatively marking it as non-cold, even if some are much smaller in
terms of bytes allocated.

This was causing us to lose sight of a very large cold context, because
we had a small non-cold one that only differed in the inlining (which we
don't consider when matching as the inlining could change or be
incomplete at that point in compilation). Likely the smaller one was
from binary with much smaller usage and therefore not yet detected as
cold.

Deduplicate the alloc contexts for a function before applying the
profile, selecting the largest one, or conservatively selecting the
non-cold one if they are the same size.

This caused a minor difference to an existing test
(memprof_loop_unroll.ll), which now only gets one message for the
duplicate context instead of 2. While here, convert to the text version
of the profile.
2025-10-31 08:48:02 -05:00
Kunqiu Chen
511c9c0648
[UTC] Support to test annotated IR (#165419)
Some analysis/transformation, e.g., predicate info/ mem ssa, insert
instruction annotations as comments, referring to
https://github.com/llvm/llvm-project/pull/165249#discussion_r2466200672.

This PR makes UTC support checking these instruction annotations with an
extra UTC option `-check-inst-comments`.

E.g., 
Before:
```LLVM
; CHECK:         [[Z_0:%.*]] = bitcast i1 [[Z]] to i1
```
After:
```LLVM
; CHECK-NEXT:  ; branch predicate info { TrueEdge: 0 Comparison: [[Z]] = and i1 [[XZ]], [[YZ]] Edge: [label [[TMP0:%.*]],label %nope], RenamedOp: [[Z]] }
; CHECK-NEXT:    [[Z_0:%.*]] = bitcast i1 [[Z]] to i1
```

This PR also regenerates all UTC-generated tests for PredicateInfo; No
MemSSA test is updated, as there are no UTC-generated tests designated
for `print<memoryssa>`.
2025-10-31 21:04:35 +08:00
Paul Walker
96c6fd36c1
[LLVM][ConstantFolding] Extend constantFoldVectorReduce to include scalable vectors. (#165437) 2025-10-31 11:14:08 +00:00
Sam Tebbs
31a0ebb840
[NFCI] Address post-merge review of #162503 (#165582) 2025-10-31 10:23:03 +00:00