712 Commits

Author SHA1 Message Date
Neil Booth
758d0fd736 Remove some unnecessary C-style statics.
Restore an assertion that arithmetic can be performed on this format.

llvm-svn: 43638
2007-11-02 15:10:05 +00:00
Chris Lattner
0083d8f38d switch some calls to SelectionDAG::getTargetNode to use
the one that takes an operand list instead of explicit
operands.  There is one left though, the more interesting
one :)

llvm-svn: 43290
2007-10-24 06:25:09 +00:00
Chris Lattner
604b2314c8 tblgen uses dynamic_cast heavily, so it needs rtti info
llvm-svn: 43126
2007-10-18 15:54:45 +00:00
Gordon Henriksen
0ab3d27641 Reverting unnecessary commit of generated files.
llvm-svn: 43095
2007-10-17 21:36:08 +00:00
Gordon Henriksen
ef5d08f4ea Switching TargetMachineRegistry to use the new generic Registry.
llvm-svn: 43094
2007-10-17 21:28:48 +00:00
Hartmut Kaiser
ec8a8d1f51 Updated VC++ build system.
Silenced some VC warnings.

I'm getting linker errors, though: unresolved externals:

llvm::Split<class llvm::BasicBlock *,struct llvm::GraphTraits<class llvm::BasicBlock *> >(class llvm::DominatorTreeBase<class llvm::BasicBlock> &,class llvm::BasicBlock *)

and

llvm::Split<struct llvm::Inverse<class llvm::BasicBlock *>,struct llvm::GraphTraits<struct llvm::Inverse<class llvm::BasicBlock *> > >(class llvm::DominatorTreeBase<class llvm::BasicBlock> &,class llvm::BasicBlock *)

Where are these defined?

llvm-svn: 43073
2007-10-17 14:56:40 +00:00
Chris Lattner
3cfb56d489 One mundane change: Change ReplaceAllUsesOfValueWith to *optionally*
take a deleted nodes vector, instead of requiring it.

One more significant change:  Implement the start of a legalizer that
just works on types.  This legalizer is designed to run before the 
operation legalizer and ensure just that the input dag is transformed
into an output dag whose operand and result types are all legal, even
if the operations on those types are not.

This design/impl has the following advantages:

1. When finished, this will *significantly* reduce the amount of code in
   LegalizeDAG.cpp.  It will remove all the code related to promotion and
   expansion as well as splitting and scalarizing vectors.
2. The new code is very simple, idiomatic, and modular: unlike 
   LegalizeDAG.cpp, it has no 3000 line long functions. :)
3. The implementation is completely iterative instead of recursive, good
   for hacking on large dags without blowing out your stack.
4. The implementation updates nodes in place when possible instead of 
   deallocating and reallocating the entire graph that points to some 
   mutated node.
5. The code nicely separates out handling of operations with invalid 
   results from operations with invalid operands, making some cases
   simpler and easier to understand.
6. The new -debug-only=legalize-types option is very very handy :), 
   allowing you to easily understand what legalize types is doing.

This is not yet done.  Until the ifdef added to SelectionDAGISel.cpp is
enabled, this does nothing.  However, this code is sufficient to legalize
all of the code in 186.crafty, olden and freebench on an x86 machine.  The
biggest issues are:

1. Vectors aren't implemented at all yet
2. SoftFP is a mess, I need to talk to Evan about it.
3. No lowering to libcalls is implemented yet.
4. Various operations are missing etc.
5. There are FIXME's for stuff I hax0r'd out, like softfp.

Hey, at least it is a step in the right direction :).  If you'd like to help,
just enable the #ifdef in SelectionDAGISel.cpp and compile code with it.  If
this explodes it will tell you what needs to be implemented.  Help is 
certainly appreciated.

Once this goes in, we can do three things:

1. Add a new pass of dag combine between the "type legalizer" and "operation
   legalizer" passes.  This will let us catch some long-standing isel issues
   that we miss because operation legalization often obfuscates the dag with
   target-specific nodes.
2. We can rip out all of the type legalization code from LegalizeDAG.cpp,
   making it much smaller and simpler.  When that happens we can then 
   reimplement the core functionality left in it in a much more efficient and
   non-recursive way.
3. Once the whole legalizer is non-recursive, we can implement whole-function
   selectiondags maybe...

llvm-svn: 42981
2007-10-15 06:10:22 +00:00
Evan Cheng
2e3d609da6 Fix typos.
llvm-svn: 42896
2007-10-12 08:39:02 +00:00
Dale Johannesen
25a00a63eb Add sqrt and powi intrinsics for long double.
llvm-svn: 42423
2007-09-28 01:08:20 +00:00
Evan Cheng
43686dad3d Rename keyword "modify" -> "implicit".
llvm-svn: 42282
2007-09-25 01:48:59 +00:00
Evan Cheng
f73fb6261b Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.

llvm-svn: 42123
2007-09-19 01:35:01 +00:00
Evan Cheng
ffd6995cc7 Bug fix and minor clean up of generated code.
llvm-svn: 42069
2007-09-17 22:26:41 +00:00
Chris Lattner
1406f7143b regenerate
llvm-svn: 42036
2007-09-17 17:40:48 +00:00
Dan Gohman
58c468fb09 Remove spurious consts. This fixes warnings with compilers that
are strict about such things.

llvm-svn: 41956
2007-09-14 20:08:19 +00:00
Evan Cheng
59c39dc197 Initial support for multi-result patterns:
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
2007-09-12 23:30:14 +00:00
Evan Cheng
c7852a689a Allow set operators with multiple destinations, i.e. (set x, y, (op a, b)).
llvm-svn: 41861
2007-09-11 19:52:18 +00:00
Evan Cheng
cef2c0efcc TableGen no longer emit CopyFromReg nodes for implicit results in physical
registers. The scheduler is now responsible for emitting them.

llvm-svn: 41781
2007-09-07 23:59:02 +00:00
Evan Cheng
20711a8b9a Always check the type of node. This prevents situations such as selecting 32-bit rotate target instruction for a 64-bit node when 64-bit pattern is missing.
llvm-svn: 41710
2007-09-04 20:18:28 +00:00
Dan Gohman
febf946ea7 Add MVT::fAny for overloading intrinsics on floating-point types.
llvm-svn: 41128
2007-08-16 21:57:19 +00:00
Rafael Espindola
66011c17d5 propagate struct size and alignment of byval arguments to the DAG
llvm-svn: 40986
2007-08-10 14:44:42 +00:00
Chandler Carruth
bebc3bb2e3 This resolves a regression of BasicAA which failed to find any memory information for overloaded intrinsics (PR1600). This resolves that issue, and improves the matching scheme to use a BitVector rather than a binary search.
llvm-svn: 40872
2007-08-06 20:57:16 +00:00
Chandler Carruth
7132e00de7 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
2007-08-04 01:51:18 +00:00
Evan Cheng
c9de9cec18 Added TargetInstrDescriptor::numDefs - num of results.
llvm-svn: 40709
2007-08-02 00:20:17 +00:00
Dan Gohman
e379f08b19 More explicit keywords.
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
Chuck Rose III
1a39a2d13d VStudio compiler errors and placing Function*->ExFunc map under ManagedStatic control.
This commit fixes two things.  One is a pair of VStudio compiler errors stemming from variables
which defined within the for loop statement and also within the body of the for loop.  I fixed these 
by renaming one of the two variables.  Additionally, I've made the Function*->ExFunc map in 
ExternalFunctions.cpp a ManagedStatic object, so that cleanup will be done on llvm_shutdown.  In repeated
uses of the interpreter, where the same Function* address may get used for completely differnet functions,
this was causing a crash.

llvm-svn: 40558
2007-07-27 18:26:35 +00:00
Dan Gohman
336718dd5c Fix a pasto in a comment.
llvm-svn: 40527
2007-07-26 15:11:00 +00:00
Christopher Lamb
2f3becc49c Have register info provide the inverse mapping of register->superregisters. PR1350
llvm-svn: 40519
2007-07-26 08:01:58 +00:00
Christopher Lamb
cde0ee5221 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
Christopher Lamb
c9ea29456a Teach TableGen about the new vector types.
llvm-svn: 40513
2007-07-26 06:41:18 +00:00
Dan Gohman
5a629d4cee A minor simplication in the generated code.
llvm-svn: 40479
2007-07-24 22:58:00 +00:00
Evan Cheng
869852b03e No need for noResults anymore.
llvm-svn: 40075
2007-07-20 00:21:23 +00:00
Evan Cheng
94b5a80b93 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Chris Lattner
6cc9a08734 Work around a bogus gcc 4.2 warning.
llvm-svn: 39993
2007-07-18 04:51:57 +00:00
Dan Gohman
10835d9c67 Eliminate an unused parameter.
llvm-svn: 39828
2007-07-13 20:16:50 +00:00
Evan Cheng
6e3c705d74 Try committing again. Add OptionalDefOperand. Remove clobbersPred.
llvm-svn: 38498
2007-07-10 18:05:01 +00:00
Evan Cheng
9835db562f ImmutablePredicateOperand is no more.
llvm-svn: 37963
2007-07-06 23:23:38 +00:00
Rafael Espindola
b567e3ffb0 Add the byval attribute
llvm-svn: 37940
2007-07-06 10:57:03 +00:00
Evan Cheng
a7d41aad4f Refactor code to add initial support for OptionalDefOperand.
llvm-svn: 37933
2007-07-06 01:05:26 +00:00
Evan Cheng
ffabff11c0 Teach DAGISelEmitter about zero_reg.
llvm-svn: 37900
2007-07-05 07:19:45 +00:00
Evan Cheng
e32e7fb40d Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
llvm-svn: 37899
2007-07-05 07:19:29 +00:00
John Criswell
2660cef6d7 Convert .cvsignore files
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
Evan Cheng
59e5e118ac One additional field in TargetRegisterDesc.
llvm-svn: 37760
2007-06-27 17:09:34 +00:00
Evan Cheng
2e887c0b84 Add immediate sub-registers.
llvm-svn: 37738
2007-06-26 20:59:16 +00:00
Dan Gohman
e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
02d1a7844a Fix a typo in a comment.
llvm-svn: 37727
2007-06-26 00:43:18 +00:00
Chris Lattner
b4777f087a silence warning when assertions are disabled.
llvm-svn: 37654
2007-06-19 06:40:46 +00:00
Dan Gohman
9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Christopher Lamb
f274efef9f Add support to tablegen for specifying subregister classes on a per register class basis.
llvm-svn: 37572
2007-06-13 22:20:15 +00:00
Evan Cheng
452a818c6a Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
llvm-svn: 37465
2007-06-06 10:14:55 +00:00