4 Commits

Author	SHA1	Message	Date
Zi Xuan Wu	9566cf16ad	[CSKY] Add codegen of select/br/cmp instruction and some frame lowering infra ... Add basic integer codegen of select/br/cmp instruction. It also includes frame lowering code such as prologue/epilogue.	2022-01-05 15:59:03 +08:00
Zi Xuan Wu	a556ec8861	[CSKY] Complete codegen of basic arithmetic and load/store operations ... Complete basic arithmetic operations such as add/sub/mul/div, and it also includes converions and some specific operations such as bswap.Add load/store patterns to generate different addressing mode instructions. Also enable some infra such as copy physical register and eliminate frame index.	2021-12-09 11:40:20 +08:00
Zi Xuan Wu	bdd7c53dc5	[CSKY] Add compressed instruction mapping between 32-bit and 16-bit instruction ... Add all CompressPat to map instructions between 16-bit and 32-bit with using the CompressInstEmitter infra. Although it's only used in asm printer, also enable it in asm parser to debug mapping when -enable-csky-asm-compressed-inst is on. Differential Revision: https://reviews.llvm.org/D115026	2021-12-06 14:04:54 +08:00
Zi Xuan Wu	cf78715cae	[CSKY] First patch to construct codegen infra and generate first add instruction ... Ooops. It constructs codegen infra and provide only basic code to generate first add instruction successfully. Differential Revision: https://reviews.llvm.org/D112206	2021-11-01 10:06:56 +08:00