2030 Commits

Author SHA1 Message Date
SpencerAbson
0adab6b1af
[AArch64][Clang] Define __ARM_NEON_SVE_BRIDGE unconditionally (#118272)
The meaning of `__ARM_NEON_SVE_BRIDGE` was changed here:
https://github.com/ARM-software/acle/pull/362

Such that it should be defined to `1` if the `arm_neon_sve_bridge.h`
header file is available, which is the case for Clang.
2024-12-04 11:32:05 +00:00
Akira Hatanaka
c8b7ec2edd
Define a diagnostic group for missing variadic macro arguments (#116855)
Make the new diagnostic group a subgroup of the following diagnostic
groups:

-Wpre-c23-compat
-Wgnu-zero-variadic-macro-arguments
-Wc++20-extensions
-Wc23-extensions

This change is needed as 5231005193afb8db01afe9a8a1aa308d25f60ba1 made
it impossible to use -Wno-gnu-zero-variadic-macro-argumentsis to silence
the warning.

rdar://139234984
2024-12-03 15:17:39 -08:00
tangaac
427be07675
[LoongArch] Support amcas[_db].{b/h/w/d} instructions. (#114189)
Two options for clang: -mlamcas & -mno-lamcas.
Enable or disable amcas[_db].{b/h} instructions.
The default is -mno-lamcas.
Only works on LoongArch64.
2024-11-27 17:36:13 +08:00
Brandon Wu
4a7dbede6b
[RISCV] Support svukte extension (#115657)
This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pull/1564,
https://lf-riscv.atlassian.net/browse/RVS-2977
The spec states that the `svukte` depends on `sv39`, but we don't have
`sv39` yet, so I didn't add it to the implied list.
2024-11-27 10:54:57 +08:00
tangaac
f4379db496
[LoongArch] Support LA V1.1 feature that div.w[u] and mod.w[u] instructions with inputs not signed-extended. (#116764)
Two options for clang
-mdiv32: Use div.w[u] and mod.w[u] instructions with input not
sign-extended.
-mno-div32: Do not use div.w[u] and mod.w[u] instructions with input not
sign-extended.
The default is -mno-div32.
2024-11-26 21:57:29 +08:00
Aaron Ballman
00770489e4
[C23] Fixed the value of BOOL_WIDTH (#117364)
The standard mandates that this returns the width of the type, which is
the number of bits in the value. For bool, that's required to be `1`
explicitly.

Fixes #117348
2024-11-25 13:01:25 -05:00
Brandon Wu
05b3d26181
[clang][RISCV] Bump RVV intrinsic to version 1.0 (#116597)
The spec:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/releases/tag/v1.0.0-rc4
Also remove __riscv_v_intrinsic_overloading since it's no longer in
spec, the overloading intrinsics should be also enabled when RVV
intrinsics are defined.
2024-11-23 01:41:12 +08:00
Pengcheng Wang
875b10f7d0 [RISCV] Support __builtin_cpu_is
We have defined `__riscv_cpu_model` variable in #101449. It contains
`mvendorid`, `marchid` and `mimpid` fields which are read via system
call `sys_riscv_hwprobe`.

We can support `__builtin_cpu_is` via comparing values in compiler's
CPU definitions and `__riscv_cpu_model`.

This depends on #116202.

Reviewers: lenary, BeMg, kito-cheng, preames, lukel97

Reviewed By: lenary

Pull Request: https://github.com/llvm/llvm-project/pull/116231
2024-11-22 22:58:54 +08:00
tangaac
1d4602070f
[LoongArch] Support LA V1.1 feature ld-seq-sa that don't generate dbar 0x700. (#116762)
Two options for clang
-mld-seq-sa: Do not generate load-load barrier instructions (dbar 0x700)
-mno-ld-seq-sa: Generate load-load barrier instructions (dbar 0x700)
The default is -mno-ld-seq-sa
2024-11-22 17:34:15 +08:00
Daniil Kovalev
3b162f73d8
[PAC][clang] Add signed GOT cc1 flag (#96160)
Add `-fptrauth-elf-got` clang cc1 flag and set `ptrauth_elf_got`
preprocessor feature and `PointerAuthELFGOT` LangOption correspondingly.
No additional checks like ensuring OS binary format is ELF are
performed: it should be done on clang driver level when a pauth-enabled
environment implying signed GOT enabled is requested.

If the cc1 flag is passed, "ptrauth-elf-got" IR module flag is set.
2024-11-19 10:20:15 +03:00
Freddy Ye
97836bed63
Reland "[X86] Support -march=diamondrapids (#113881)" (#116564)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-18 10:40:32 +08:00
Freddy Ye
90e92239bd
Revert "[X86] Support -march=diamondrapids (#113881)" (#116563)
This reverts commit 826b845c9e97448395431be3e4e5da585bd98c5e.
2024-11-18 08:45:28 +08:00
Freddy Ye
826b845c9e
[X86] Support -march=diamondrapids (#113881)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-18 08:31:17 +08:00
SpencerAbson
748b028540
[AArch64] Make +sve2-aes an alias of +sve2+sve-aes (#116026)
This patch essentially re-lands
https://github.com/llvm/llvm-project/pull/114293 with the following
fixups

- `nosve2-aes` should disable the backend feature `FeatureSVEAES` such
that the set of existing instructions that this removes is unchanged.
- FMV dependencies now use the autogenerated `ExtensionDepencies`
structure (since https://github.com/llvm/llvm-project/pull/113281) so we
do not require the change to `AArch64FMV.td`.
2024-11-14 11:04:04 +00:00
Alexandros Lamprineas
3cc852ece4
[FMV][AArch64] Expand feature dependencies using AArch64::ExtensionSet. (#113281)
Currently we maintain a hand written list of subtarget features which we
are implied for a given FMV feature. It is more robust to expand such
dependencies using ExtensionDependency from TargetParser, since that is
generated by tablegen. For this to work each FMV feature must have a
corresponding SubtargetFeature in place. FMV features which didn't
satisfy this criteria have been removed from the ACLE specification
(https://github.com/ARM-software/acle/pull/315). However, I deliberately
marked the ArchExtKind in FMVInfo structure as std::optional in case we
decide to break this rule in the future.

I have also added the missing dependencies:
 * FEAT_DPB2 -> FEAT_DPB
 * FEAT_FlagM2 -> FEAT_FlagM
2024-11-12 16:01:35 +00:00
Feng Zou
eddb79d56d
[X86][AMX] Support AMX-TF32 (#115625)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-11 15:24:18 +08:00
Phoebe Wang
8f4401374c
Reland "[X86][AMX] Support AMX-AVX512" (#115581)
Resolve compile fail without SSE2.
2024-11-09 13:26:10 +08:00
Alan Zhao
ff22515430
Revert "[X86][AMX] Support AMX-AVX512" (#115570)
Reverts llvm/llvm-project#114070

Reason: Causes `immintrin.h` to fail to compile if `-msse` and
`-mno-sse2` are passed to clang:
https://github.com/llvm/llvm-project/pull/114070#issuecomment-2465926700
2024-11-08 16:15:02 -08:00
SpencerAbson
bbcd35270e
Revert "[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114… (#115539)
…293)"

This reverts commit da9499ebfb323602c42aeb674571fe89cec20ca6.
2024-11-08 20:19:31 +00:00
SpencerAbson
da9499ebfb
[AArch64] Reduce +sve2-aes to an alias of +sve-aes+sve2 (#114293)
This patch introduces the amended feature flag for
[FEAT_SVE_AES](https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-0-architecture-extension?lang=en#md457-the-armv90-architecture-extension__feat_FEAT_SVE_AES),
'**sve-aes**'. The existing flag associated with this feature,
'sve2-aes' must be retained as an alias of 'sve-aes' and 'sve2' for
backwards compatibility.

The
[ACLE](https://github.com/ARM-software/acle/blob/main/main/acle.md#aes-extension)
documents `__ARM_FEATURE_SVE2_AES`, which was previously defined to 1
when

> there is hardware support for the SVE2 AES (FEAT_SVE_AES) instructions
and if the associated ACLE intrinsics are available.

The front-end has been amended such that it is compatible with +sve2-aes
and +sve2+sve-aes.
2024-11-08 15:07:05 +00:00
Phoebe Wang
58a17e1bbc
[X86][AMX] Support AMX-AVX512 (#114070) 2024-11-08 16:25:16 +08:00
T-Tie
c17a914675
[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)
Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url)
Specification link(Ssdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)
2024-11-08 15:01:51 +08:00
Phoebe Wang
c72a751dab
[X86][AMX] Support AMX-TRANSPOSE (#113532)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-11-01 16:45:03 +08:00
Aaron Ballman
af7c58b7ea
Remove support for RenderScript (#112916)
See
https://discourse.llvm.org/t/rfc-deprecate-and-eventually-remove-renderscript-support/81284
for the RFC
2024-10-28 12:48:42 -04:00
dong-miao
75c75fc16e
[RISCV]Add svvptc extension (#113882) 2024-10-28 22:54:51 +11:00
Alex Bradbury
35f6cc6af0
[RISCV] Add the Sha extension (#113820)
This was introduced in the now-ratified RVA23 profile (and also added to
the RVA22 text) as a simple way of referring to H plus the set of
supervisor extensions required by RVA23.
https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

This patch simply defines the extension. The next patch will adjust the
RVA23 profile to use it, and at that point I think we will be ready to
mark RVA23 as non-experimental.

Note that I haven't made it so if you enable all extensions that
constitute Sha, Sha is implied. Per #76893 (adding 'B'), the concern is
making this implication might break older external assemblers. Perhaps
this is less of a concern given the relative frequency of
`-march=${foo}_zba_zbb_zbs` vs the collection of H extensions. If we did
want to add that implication, we'd probably want to add it in a separate
patch so it can be easily reverted if found to cause problems.
2024-10-28 07:42:33 +00:00
Dan Gohman
1bc2cd98c5
[WebAssembly] Enable nontrapping-fptoint and bulk-memory by default. (#112049)
We were prepared to enable these features [back in February], but they
got pulled for what appear to be unrelated reasons. So let's have
another try at enabling them!

Another motivation here is that it'd be convenient for the [Lime1
proposal] if "lime1" is close to a subset of "generic" (missing only
for extended-const).

[back in February]:
https://github.com/WebAssembly/tool-conventions/issues/158#issuecomment-1931119512
[Lime1 proposal]: https://github.com/llvm/llvm-project/pull/112035
2024-10-25 13:52:51 -07:00
Alex Bradbury
2c0b34852a
[RISCV] Mark pointer masking extensions as non-experimental (#113618)
These extensions were ratified very recently.

<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions>

I've ensured we have definitions for all extensions in the document
<https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link>.
There are no additional CSRs.
2024-10-25 12:24:50 +01:00
dong-miao
ed6ddffb58
[RISCV] Add Smrnmi extension (#111668)
This commit has completed the Extension for Resumable Non Maskable
Interrupts, adding four CRSs and one Trap-Return instruction.
Specification link:["Smrnmi"
Extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc)

---------

Co-authored-by: Sam Elliott <sam@lenary.co.uk>
2024-10-25 18:41:21 +11:00
Freddy Ye
c4248fa3ed
[X86] Support MOVRS and AVX10.2 instructions. (#113274)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
2024-10-25 09:00:19 +08:00
Alex Crichton
c2293b33dd
[WebAssembly] Implement the wide-arithmetic proposal (#111598)
This commit implements the [wide-arithmetic] proposal which has recently
reached phase 2 in the WebAssembly proposals process. The goal here is
to implement support in LLVM for emitting these instructions which are
gated behind a new feature flag by default. A new `wide-arithmetic`
feature flag is introduced which gates these four new instructions from
being emitted.

Emission of each instruction itself is relatively simple given LLVM's
preexisting lowering rules and infrastructure. The main gotcha is that
due to the multi-result nature of all of these instructions it needed
the lowerings to be implemented in C++ rather than in TableGen.

[wide-arithmetic]: https://github.com/WebAssembly/wide-arithmetic
2024-10-23 11:39:58 -07:00
tangaac
5b9c76b6e7
[LoongArch] Support LoongArch-specific amswap[_db].{b/h} and amadd[_db].{b/h} instructions (#113255)
Two options for clang: -mlam-bh & -mno-lam-bh.
Enable or disable amswap[__db].{b/h} and amadd[__db].{b/h} instructions.
The default is -mno-lam-bh.
Only works on LoongArch64.
2024-10-23 16:03:15 +08:00
Abhina Sree
46dc91e7d9
[SystemZ][z/OS] Add new openFileForReadBinary function, and pass IsText parameter to getBufferForFile (#111723)
This patch adds an IsText parameter to the following getBufferForFile,
getBufferForFileImpl. We introduce a new virtual function
openFileForReadBinary which defaults to openFileForRead except in
RealFileSystem which uses the OF_None flag instead of OF_Text.

The default is set to OF_Text instead of OF_None, this change in value
does not affect any other platforms other than z/OS. Setting this
parameter correctly is required to open files on z/OS in the correct
encoding. The IsText parameter is based on the context of where we open
files, for example, in the ASTReader, HeaderMap requires that files
always be opened in binary even though they might be tagged as text.
2024-10-21 08:20:22 -04:00
Hans
4ddea298e6
[clang-cl]: Add /std:c++23preview and update _MSVC_LANG for C++23 (#112378)
As discussed in
https://discourse.llvm.org/t/clang-cl-adding-std-c-23preview/82553
2024-10-16 10:06:43 +02:00
c8ef
ab6ec7ab14
[clang] Mark __builtin_convertvector and __builtin_shufflevector as constexpr. (#112129)
Closes #107985.

LanguageExtensions.rst states that `__builtin_shufflevector` and
`__builtin_convertvector` can be evaluated as constants, but this is not
reflected in Butiltins.td. This patch aligns these two.
2024-10-15 00:09:36 +08:00
Michał Górny
387b37af1a
[LLVM] [Clang] Support for Gentoo *t64 triples (64-bit time_t ABIs) (#111302)
Gentoo is planning to introduce a `*t64` suffix for triples that will be
used by 32-bit platforms that use 64-bit `time_t`. Add support for
parsing and accepting these triples, and while at it make clang
automatically enable the necessary glibc feature macros when this suffix
is used.

An open question is whether we can backport this to LLVM 19.x. After
all, adding new triplets to Triple sounds like an ABI change — though I
suppose we can minimize the risk of breaking something if we move new
enum values to the very end.
2024-10-14 11:18:04 +00:00
YunQiang Su
5bf81e53db
Clang: Support minimumnum and maximumnum intrinsics (#96281)
We just introduce llvm.minimumnum and llvm.maximumnum intrinsics support
to llvm. Let's support them in Clang.

See: #93033
2024-10-14 15:49:01 +08:00
cor3ntin
75611caff4
[Clang] Improve type traits recognition in __has_builtin (#111516)
`__has_builtin` was relying on reversible identifiers and string
matching to recognize builtin-type traits, leading to some newer type
traits not being recognized.

Fixes #111477
2024-10-08 23:03:32 +02:00
Jonathan Thackray
d0756caedc
[ARM][AArch64] Introduce the Armv9.6-A architecture version (#110825)
This introduces the Armv9.6-A architecture version, including the
relevant command-line option for -march.

More details about the Armv9.6-A architecture version can be found at:
  * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2024
  * https://developer.arm.com/documentation/ddi0602/2024-09/
2024-10-04 10:12:41 +01:00
Alex Bradbury
614aeda93b
[RISCV] Mark Zacas as non-experimental (#109651)
The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. The
ABI issue has been resolved by #101023 so I believe there's no known
barrier to moving Zacas to non-experimental.
2024-09-25 06:14:43 +01:00
eddyz87
eabc8857e7
[BPF] make __BPF_FEATURE_MAY_GOTO available for cpuv1 (#108071)
For some reason `__BPF_FEATURE_MAY_GOTO` is available for CPUs v{2,3,4}
but is not available for CPU v1. This limitation is arbitrary:
- the instruction is never produced by LLVM backend;
- on Linux Kernel side this instruction is available in kernels that
also support CPUv4.

Hence, it is more consistent to either always allow
`__BPF_FEATURE_MAY_GOTO` or only allow it for CPUv4.
2024-09-24 11:46:33 +03:00
Rainer Orth
39e30508a7
[Driver][Sparc] Default to -mcpu=v9 for 32-bit Linux/sparc64 (#109278)
While working on supporting PR #109101 on Linux/sparc64, I was reminded
that `clang -m32` still defaults to generating V8 code, although the
64-bit kernel requires a V9 CPU.

This patch corrects that.

Tested on `sparc64-unknown-linux-gnu`, `x86_64-pc-linux-gnu`,
`sparcv9-sun-solaris2.11`, and `amd64-pc-solaris2.11`.
2024-09-21 19:53:35 +02:00
Chris B
4d621025d4
[HLSL] Warn about incomplete language support (#108894)
This adds a warning about incomplete language mode support before HLSL
202x. This is the last change in the sequence to fix and make HLSL 202x
the default mode for Clang (#108044).


Fixes #108044
2024-09-20 16:41:15 -05:00
Alexandros Lamprineas
b1d7694c12
[AArch64] Add missing ACLE predefined macros and update __ARM_ACLE. (#108857)
Adds __ARM_ACLE_VERSION and __FUNCTION_MULTI_VERSIONING_SUPPORT_LEVEL
as defined here https://github.com/ARM-software/acle/pull/301 and
here https://github.com/ARM-software/acle/pull/302.

Also bumps __ARM_ACLE to 202420.
2024-09-17 11:07:07 +01:00
Chris B
488640389f
[HLSL] Align language modes on 202x as default (#108662)
As captured in issue #108044, HLSL 202x is the target language mode for
conformance for Clang. Earlier language modes will be a best effort and
prioritized after 2020x. To make this easier and reduce our testing
complexity we want to make 202x the default language mode now, and align
all earlier modes to match 202x (except where we explicitly deviate).

This change has the following concrete changes:
* All older language modes gain `CPlusPlus11` as a base
* The default language mode for HLSL sources is changed to 202x
* A few test cases are updated to resolve differences in generated
diagnostics.

Second to last change for  #108044
2024-09-16 17:17:15 -05:00
Chris B
2222e27d9e
[HLSL] Add HLSL 202y language mode (#108437)
This change adds a new HLSL 202y language mode. Currently HLSL 202y is
planned to add `auto` and `constexpr`.

This change updates extension diagnostics to state that lambadas are a
"clang HLSL" extension (since we have no planned release yet to include
them), and that `auto` is a HLSL 202y extension when used in earlier
language modes.

Note: This PR does temporarily work around some differences between HLSL
2021 and 202x in Clang by changing test cases to explicitly specify
202x. A subsequent PR will update 2021's language flags to match 202x.
2024-09-13 16:11:19 -05:00
Ganesh
02e4186d0b
[X86] AMD Zen 5 Initial enablement (#107964)
This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
2024-09-13 17:45:33 +01:00
Jim Lin
dee058f9e3
[RISCV] Emit predefined macro __riscv_cmodel_large for large code model (#108131)
Co-authored-by: patrick <patrick@andestech.com>
2024-09-13 10:37:48 +08:00
Sean Perry
e62bf7cd0b
[z/OS] Set the default arch for z/OS to be arch10 (#89854)
The default arch level on z/OS is arch10. Update the code so z/OS has
arch10 without changing the default for zLinux.
2024-09-09 15:24:16 -04:00
Alex Rønne Petersen
b55186eefd
[clang][Driver] Define soft float macros for PPC. (#106012)
Fixes #105972.

Co-authored-by: Qiu Chaofan <qcf@ecnelises.com>
2024-09-04 10:07:35 +08:00