523 Commits

Author SHA1 Message Date
Matt Arsenault
6f8e7c11cf
AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (#117379)
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
2024-11-25 09:42:07 -08:00
Matt Arsenault
cd20fc0772
AMDGPU: Remove wavefrontsize64 feature from dummy target (#117410)
This is a refinement for the existing hack. With this,
the default target will have neither wavefrontsize feature
present, unless it was explicitly specified. That is,
getWavefrontSize() == 64 no longer implies +wavefrontsize64.
getWavefrontSize() == 32 does imply +wavefrontsize32.

Continue to assume the value is 64 with no wavesize feature.
This maintains the codegenable property without any code
that directly cares about the wavesize needing to worry about it.

Introduce an isWaveSizeKnown helper to check if we know the
wavesize is accurate based on having one of the features explicitly
set, or a known target-cpu.

I'm not sure what's going on in wave_any.s. It's testing what
happens when both wavesizes are enabled, but this is treated
as an error in codegen. We now treat wave32 as the winning
case, so some cases that were previously printed as vcc are now
vcc_lo.
2024-11-23 09:27:47 -08:00
Matt Arsenault
8b087d6422
AMDGPU: Move default wavesize hack for disassembler (#117422)
You cannot adjust the disassembler's subtarget. llvm-mc passes
the originally constructed MCSubtargetInfo around, rather than
querying the pointer in the disassembler instance.
2024-11-23 09:24:44 -08:00
Matt Arsenault
01c9a14ccf
AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)
These use a new VOP3PX encoding for the v_mfma_scale_* instructions,
which bundles the pre-scale v_mfma_ld_scale_b32. None of the modifiers
are supported yet (op_sel, neg or clamp).

I'm not sure the intrinsic should really expose op_sel (or any of the
others). If I'm reading the documentation correctly, we should be able
to just have the raw scale operands and auto-match op_sel to byte
extract patterns.

The op_sel syntax also seems extra horrible in this usage, especially with the
usual assumed op_sel_hi=-1 behavior.
2024-11-21 08:51:58 -08:00
Jay Foad
ade0750e35
[AMDGPU] Fix some cache policy checks for GFX12+ (#116396)
Fix coding errors found by inspection and check that the swz bit still
serves to prevent merging of buffer loads/stores on GFX12+.
2024-11-21 08:22:59 +00:00
Matt Arsenault
a6fc489bb7
AMDGPU: Add gfx950 subtarget definitions (#116307)
Mostly a stub, but adds some baseline tests and
tests for removed instructions.
2024-11-18 10:41:14 -08:00
Janek van Oirschot
bd9145c8c2
Reapply [AMDGPU] Avoid resource propagation for recursion through multiple functions (#112251)
I was wrong last patch. I viewed the `Visited` set purely as a possible
recursion deterrent where functions calling a callee multiple times are
handled elsewhere. This doesn't consider cases where a function is
called multiple times by different callers still part of the same call
graph. New test shows the aforementioned case.

Reapplies #111004, fixes #115562.
2024-11-15 18:40:05 +00:00
Kazu Hirata
be187369a0
[AMDGPU] Remove unused includes (NFC) (#116154)
Identified with misc-include-cleaner.
2024-11-13 21:10:03 -08:00
Ethan Luis McDonough
e8c07f7458
[MC][AMDGPU] Support .reloc BFD_RELOC_{NONE,32,64} (#114617)
Emitting BFD_RELOC_* reloc directives can cause internal errors on
AMDGPU.
2024-11-13 16:07:33 -06:00
Shilei Tian
de0fd64bed
[AMDGPU] Introduce a new generic target gfx9-4-generic (#115190)
This patch introduces a new generic target, `gfx9-4-generic`. Since it doesn’t support FP8 and XF32-related instructions, the patch includes several code reorganizations to accommodate these changes.
2024-11-12 23:11:05 -05:00
Kazu Hirata
4048c64306
[llvm] Remove redundant control flow statements (NFC) (#115831)
Identified with readability-redundant-control-flow.
2024-11-12 10:09:42 -08:00
Sergei Barannikov
eeb987f6f3
[MC] Make generated MCInstPrinter::getMnemonic const (NFC) (#114682)
The value returned from the function depends only on the instruction opcode.

As a drive-by, change the type of the argument to const-reference.
2024-11-03 20:37:26 +03:00
Fangrui Song
facdae62b7 [MCInstPrinter] Make printRegName non-const
Similar to printInst. printRegName may change states (e.g. #113834).
2024-10-29 19:14:54 -07:00
Carl Ritson
076aac59ac
[AMDGPU] Add a new target for gfx1153 (#113138) 2024-10-23 12:56:58 +09:00
Janek van Oirschot
a18826d75c
[AMDGPU] Create local KnownBits in case DenseMap gets invalidated (#111568)
KnownBits retrieved from DenseMap may invalidate if insertion requires a
(re)growth.

Fixes https://github.com/llvm/llvm-project/issues/110930
2024-10-22 16:05:07 +01:00
Jay Foad
8d13e7b8c3
[AMDGPU] Qualify auto. NFC. (#110878)
Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)
2024-10-03 13:07:54 +01:00
Janek van Oirschot
c897c13dde
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
Converts AMDGPUResourceUsageAnalysis pass from Module to MachineFunction
pass. Moves function resource info propagation to to MC layer (through
helpers in AMDGPUMCResourceInfo) by generating MCExprs for every
function resource which the emitters have been prepped for.

Fixes https://github.com/llvm/llvm-project/issues/64863
2024-09-30 11:43:34 +01:00
Craig Topper
fd50cdfb94 [AMDGPU] Use MCRegister. NFC 2024-09-28 11:40:25 -07:00
Jun Wang
cd5f5b7690
[AMDGPU][MC] Implement fft and rotate modes for ds_swizzle_b32 (#108064)
In addition to the basic mode, the ds_swizzle_b32 is supposed to support
two specific modes: fft and rotate. This patch implements those two
modes.
2024-09-27 10:18:34 -07:00
Jay Foad
73b8074e68
[AMDGPU] Do not use APInt for simple 64-bit arithmetic. NFC. (#109414) 2024-09-20 13:45:04 +01:00
Fangrui Song
c19326cb84 [MC] Replace HasAggressiveSymbolFolding with SetDirectiveSuppressesReloc. NFC
The variable and its comment could lead to confusion (AMDGPU
unnecessarily set it).
2024-08-15 13:29:47 -07:00
Janek van Oirschot
bfce1aae76
[AMDGPU] MCExpr printing helper with KnownBits support (#95951)
Walks over the MCExpr and uses KnownBits to deduce whether an expression
is known and if so, prints said known value. Should support the most
common MCExpr cases for AMDGPU metadata.
2024-08-15 13:43:13 +01:00
Ivan Kosarev
f0fe6c66cb
[AMDGPU][NFC] Rename isHi() to isHi16Reg() for clarity. (#103888)
And declare it to take an MCRegister.

Also rename related entities and remove a comment for the function that
depending on its purpose is either irrelevant or misleading.
2024-08-14 17:04:15 +01:00
Ivan Kosarev
c7107ca7f8
[AMDGPU][NFCI] Mark AGPRs and VGPRs with different flags in HWEncoding. (#102650)
Simplifies checks for AGPRs and VGPRs and makes them more explicit and
less fragile.
2024-08-12 13:06:19 +01:00
Sam James
8f39502b85
[AMDGPU] Include <cstdint> in AMDGPUMCTargetDesc (#101766) 2024-08-03 09:36:43 +04:00
Matt Arsenault
d2b6a8ee67
AMDGPU: Fix asserting when trying to print scc (#101175)
This is printable using inline assembly. Also we should
handle using scc directly as instruction operands.
2024-07-30 17:41:13 +04:00
Sergei Barannikov
25bea3eb03
[MC] Forward declare ELFObjectWriter (#100989) 2024-07-30 10:40:40 +03:00
Ivan Kosarev
5bd3aef5e2
[AMDGPU] Use a generic printer for NamedIntOperands. (#100399)
This includes simplifying printing dmask modifiers where we don't need
to mask the value to print.

Part of <https://github.com/llvm/llvm-project/issues/62629>.
2024-07-29 09:54:05 +01:00
Ivan Kosarev
7a3bc44c89
[AMDGPU][MC][NFCI] Eliminate printU4ImmDecOperand(). (#100589)
This is hoped to make things a bit safer not masking the value to print
and to make the logic in printDPPCtrl() a bit more explicit.

Part of <https://github.com/llvm/llvm-project/issues/62629>.
2024-07-26 10:10:30 +01:00
Ivan Kosarev
24a18aafa3
[AMDGPU] Simplify printing row/bank_mask modifiers. (#100575)
And fix a codegen test to use mask values that fit their encoding
fields.

Part of <https://github.com/llvm/llvm-project/issues/62629>.
2024-07-25 16:44:44 +01:00
Ivan Kosarev
430cf6537b
[AMDGPU][NFCI] Declare offset0/1 operands to be i32. (#100560)
Being of type i8 makes them signed, which they aren't, and requires
extra work masking them on verbalisation.

Part of <https://github.com/llvm/llvm-project/issues/62629>.
2024-07-25 14:32:19 +01:00
Fangrui Song
c473e75ade MCAssmembler: Move ELFHeaderEFlags to ELFObjectWriter
Now that MCELFStreamer can access ELFObjectWriter (commit
70c52b62c5669993e341664a63bfbe5245e32884), we can move ELFHeaderEFlags
there.
2024-07-22 18:20:18 -07:00
Fangrui Song
70c52b62c5 [MC] Export llvm::ELFObjectWriter
Similar to commit 28fcafb50274be2520117eacb0a886adafefe59d (2011) for
MachObjectWriter and commit 9539a7796094ff5fb59d9c685140ea2e214b945c for
WinCOFFObjectWriter.

MCELFStreamer can now access ELFObjectWriter directly without adding
ELF-specific markGnuAbi (https://reviews.llvm.org/D97976) and
setOverrideABIVersion to MCObjectWriter.

A few member variables have to be made public since we cannot use a
friend declaration for ELFWriter.
2024-07-22 16:18:25 -07:00
Fangrui Song
6717dc5c47 *AsmBackend.cpp: Include StringSwitch.h
They currently get the header from MCLinkerOptimizationHint.h, which
will be removed from MCAssembler.h.
2024-07-21 11:17:19 -07:00
Fangrui Song
7f017f0ab4 [MC] Drop unnecessary MCSymbol::setExternal calls for ELF
Similar to e4c360a897fe062914519d331e8f1e28b2b1fbfd (2020).
2024-07-21 10:49:25 -07:00
Fangrui Song
8f14e39e59 [MC] Remove unnecessary isVerboseAsm from Target::AsmTargetStreamerCtorTy
The parameter is confusing as it duplicates MCStreamer::isVeboseAsm
(initialized from MCTargetOptions::AsmVerbose). After
233cca169237b91d16092c82bd55ee6a283afe98, no in-tree target uses the
parameter.
2024-07-21 10:19:17 -07:00
Jay Foad
63fae3ed65
[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298) 2024-07-17 21:11:00 +01:00
Jay Foad
74b87b02d2 [AMDGPU] Fix and add namespace closing comments. NFC. 2024-07-16 16:56:31 +01:00
Fangrui Song
057f28be3e [MC] Remove unused MCAsmLayout declarations and includes 2024-07-01 17:47:13 -07:00
Fangrui Song
e25e8003ca MCExpr::evaluateAsRelocatable: replace the MCAsmLayout parameter with MCAssembler
Continue the MCAsmLayout removal work started by 67957a45ee1ec42ae1671cdbfa0d73127346cc95.
2024-07-01 16:23:43 -07:00
Fangrui Song
f22af401a4 [MC,AMDGPU] Migrate MCAsmLayout to MCAssembler 2024-07-01 16:07:48 -07:00
Fangrui Song
7c83b7ef17 [MC] Remove two unused parameters from MCAsmBackend::fixupNeedsRelaxation
fixupNeedsRelaxation is a simple implementation for
fixupNeedsRelaxationAdvanced. Its users do not utilize MCAsmLayout or
MCRelaxableFragment.

Follow-up to 22c7317f1e954b34a46640db5d509bae1c633348
("[MC] Remove the MCAsmLayout parameter from relocation related functions").
2024-07-01 14:11:29 -07:00
Janek van Oirschot
17eaa23f7e
[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)
Enables MCExpr for HSAMetadata, particularly, HSAMetadata's msgpack format.
2024-06-26 16:39:08 +01:00
Ivan Kosarev
13ed349c44
[AMDGPU][NFC] Rename AMDGPUVariadicMCExpr to AMDGPUMCExpr. (#96618)
Some of our custom expressions are not variadic and there seems to be
little benefit in mentioning the variadic nature of expression nodes in
the name anyway.
2024-06-25 15:32:09 +01:00
Ivan Kosarev
162386693f
[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)
Our other tools support them, so we want them in LLVM
assembler/disassembler too.
2024-06-18 15:44:14 +01:00
Pierre van Houtryve
9ab601fa53 Reland "[NFC][AMDGPU] Do not flush after printing every instruction (#95237)"
It's very expensive and doesn't achieve anything.

I one test I did, it saves almost 10s on a 2m23s build, bringing it down
to 2m15s using a downstream branch.
2024-06-13 08:30:06 +02:00
pvanhout
04c4cf45fa Revert "[NFC][AMDGPU] Do not flush after printing every instruction (#95237)"
This reverts commit ad9fe3b2a949fb3379e0a1bafbcd2ca81f5fa414.
2024-06-12 15:24:21 +02:00
Pierre van Houtryve
ad9fe3b2a9
[NFC][AMDGPU] Do not flush after printing every instruction (#95237)
It's very expensive and doesn't achieve anything.

I one test I did, it saves almost 10s on a 2m23s build, bringing it down
to 2m15s using a downstream branch.
2024-06-12 14:57:41 +02:00
Shilei Tian
1ca0055f45
[AMDGPU] Add a new target gfx1152 (#94534) 2024-06-06 12:16:11 -04:00
Konstantin Zhuravlyov
775f1cd34d
AMDGPU: Add gfx12-generic target (#93875) 2024-05-31 12:46:44 -04:00