6 Commits

Author	SHA1	Message	Date
Liao Chunyu	f4d2f7a3b7	[RISCV] Codegen support for XCVbi extension (#89719) ... spec: https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst#immediate-branching-operations Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @NandniJamnadas, @PaoloS02, @simonpcook, @xingmingjie, @realqhc, @PhilippvK,@melonedo	2024-05-08 11:22:16 +08:00
Craig Topper	0f4c9c016c	[RISCV] Replace RISCV->RISC-V in strings. ... To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. D146449 already updated comments. Strings may have more user impact. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146451	2023-03-27 09:50:17 -07:00
Craig Topper	29463612d2	[RISCV] Replace RISCV -> RISC-V in comments. NFC ... To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. More patches will follow. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146449	2023-03-27 09:50:17 -07:00
Craig Topper	6732896bbf	[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination. ... The existing code was incorrect if we had more than one conditional branch instruction in a basic block. Though I don't think that will occur, using analyzeBranch detects that as an unsupported case. Overall this results in simpler code in RISCVRedundantCopyElimination. Reviewed By: reames, kito-cheng Differential Revision: https://reviews.llvm.org/D132347	2022-08-29 09:05:53 -07:00
Craig Topper	abce7acebd	[RISCV] Remove impossible TODO in RISCVRedundantCopyElimination. NFC ... If there are multiple conditional branches we shouldn't do any optimization.	2022-08-21 13:18:02 -07:00
Craig Topper	1d8bbe3d25	[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. ... Using AArch64's original implementation for reference, this patch implements a pass to remove unneeded copies of X0. This pass runs after register allocation and looks to see if a register is implied to be 0 by a branch in the predecessor basic block. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D118160	2022-02-04 10:43:46 -08:00