6009 Commits

Author SHA1 Message Date
Markus Böck
2a30bfcef3
[mlir] Improve error message when number of operands and types differ (#118488)
If using a variadic operand, the error message given if the number of
types and operands do not match would be along the lines of:
```
3 operands present, but expected 2
```

This error message is confusing for multiple reasons, particular for
beginners:
* If the intention is to have 3 operands, it does not point out why it
expects 2. The user may actually just want to add a type to the type
list
* It reads as if a verifier error rather than a parser error, giving the
impression the Op only supports 2 operands.

This PR attempts to improve the error message by first noting the issue
("number of operands and types mismatch") and mentioning how many
operands and types it received.
2024-12-04 09:36:05 +01:00
Kunwar Grover
a201ba1b57
[mlir][Vector] Add support for 0-d shapes in extract-shape_cast folder (#116650)
The extract <-> shape cast folder was conservatively asserting and
failing on 0-d vectors. This pr fixes this.

This pr also adds more tests for 0d cases and updates related tests to
better reflect what they test.
2024-12-04 00:03:50 +00:00
Ian Wood
fcfdabfea1
[MLIR] Improve compose expand(collapse) pattern (#117768)
If expand(collapse) has a dimension that gets collapsed and then
expanded to the same shape, the pattern would fail to canonicalize this
to a single collapse shape. Line 341 was changed because the
expand(collapse) could be a reinterpret-cast like sequence where the
shapes differ but the rank is the same. This cannot be represented by a
single `collapse_shape` op.

Signed-off-by: Ian Wood <ianwood2024@u.northwestern.edu>
2024-12-02 16:34:26 +00:00
Andrzej Warzyński
b27d97bef7
[mlir][tensor] Add test for invalid tensor.unpack + update error msg (#118275)
Adds a new test for invalid `tensor.unpack` operations where the output
rank does not match the expected rank (input rank + num inner tile
sizes). For example:

```mlir
tensor.unpack %output
  inner_dims_pos = [0, 1]
  inner_tiles = [32, 16]
  into %input : tensor<64x32x16xf32> -> tensor<256x128xf32>
```

In addition, updates the corresponding error message to make it more
informative:

BEFORE:
```mlir
error: packed rank must equal unpacked rank + tiling factors}
```

AFTER:
```mlir
error: packed rank != (unpacked rank + num tiling factors), got 3 != 4
```
2024-12-02 15:33:05 +00:00
Andrzej Warzyński
38098b486e
[mlir][vector] Disable CompressStoreOp/ExpandLoadOp for scalable vectors (#117538)
These operations were introduced as counterparts to the following LLVM
intrinsics:

  * `@llvm.masked.expandload.*`,
  * `@llvm.masked.compressstore.*`.

Currently, there is minimal test coverage for scalable vector use cases
involving these Ops (both LLVM and MLIR). Additionally, the verifier is
flawed  - it incorrectly allows mixing fixed-width and scalable vectors.

To address these issues, scalable vector support for these Ops is being
disabled for now. This decision can be revisited if a clear need arises
for their use with scalable vectors in the future.
2024-11-29 16:13:09 +00:00
Andrzej Warzyński
5540eac4e5
[mlir][vector] Disable from_elements for scalable vectors (#117868)
Disables `vector.from_elements` for scalable vectors. Given that the
length of scalable vectors is unknown at compile time, the semantics of
this Op are unclear in this context.
2024-11-29 11:51:45 +00:00
lonely eagle
26ffca0843
[mlir][gpu]add AffineScope to gpu.func op. (#118010)
This PR in order to solve the following problem.
https://github.com/llvm/llvm-project/pull/117721.
To efficiently implement the thread-to-data mapping relationship, I
introduced AffineScope in gpu.func(Data or thread layout).
2024-11-29 11:10:00 +01:00
Andrzej Warzyński
aa9d368690
[mlir][linalg] Relax scalable vectorization restrictions (#117991)
Currently, the Linalg vectorizer disallows non-trailing parallel
dimensions to be scalable, e.g., `vector_sizes [[8], 1]` (*), for cases
like:

```mlir
%0 = linalg.fill ins(%arg0 : f32) outs(%A : tensor<?x?xf32>) -> tensor<?x?xf32>
```

This restriction exists to avoid generating "scalable" arrays of
aggregates, which LLVM does not support (multi-dim vectors are lowered
into arrays of aggregates at the LLVM level).

This patch relaxes that restriction when the trailing parallel vector
dimension is `1`, e.g., for `vector_sizes [[8], 1]`. Such cases are safe
since trailing unit dimensions can be collapsed. This relaxation is
necessary to support scalable vectorization for tensor.pack, where inner
tile sizes are `[8]` (scalable) and `1` (scalar).

(*) Transform Dialect notation
2024-11-29 07:43:10 +00:00
Abhishek Varma
d83148f9b9
[MLIR][Affine] Update ::fold() to have constant basis attr for affine.delinearize_index/linearize_index (#117572)
-- This commit updates `::fold()` to have constant(CST)
   attribute for affine.delinearize_index/linearize_index op's basis
   wherever applicable.
-- Essentially the code checks if the mixed basis OpFoldResult
   set contains any constant SSA value and converts it to a constant
   integer instead.

Signed-off-by: Abhishek Varma <abhvarma@amd.com>
2024-11-29 10:22:23 +05:30
Frank Schlimbach
79eb406a67
[mlir][mesh, MPI] Mesh2mpi (#104566)
Pass for lowering `Mesh` to `MPI`.
Initial commit lowers `UpdateHaloOp` only.
2024-11-28 09:38:38 +00:00
Kareem Ergawy
2918a47f42
[mlir][OpenMP] Annotate private vars with map_idx when needed (#116770)
This PR extends the MLIR representation for `omp.target` ops by adding a
`map_idx` to `private` vars. This annotation stores the index of the map
info operand corresponding to the private var. If the variable does not
have a map operand, the `map_idx` attribute is either not present at all
or its value is `-1`.

This makes matching the private variable to its map info op easier (see
https://github.com/llvm/llvm-project/pull/116576 for usage).
2024-11-28 05:15:33 +01:00
lialan
1669ac434c
[MLIR] Refactor mask compression logic when emulating vector.maskedload ops (#116520)
This patch simplifies and extends the logic used when compressing masks
emitted by `vector.constant_mask` to support extracting 1-D vectors from
multi-dimensional vector loads. It streamlines mask computation, making
it applicable for multi-dimensional mask generation, improving the
overall handling of masked load operations.
2024-11-27 13:22:13 -08:00
Clément Fournier
b6ab04c69c
[mlir][arith] Fix arith maxnumf/minnumf folder (#114595)
Fix #114594 
#### Context

[IEEE754-2019](https://ieeexplore.ieee.org/document/8766229) Sec 9.6
defines 2 minimum and 2 maximum operations. They are termed
- `maximum` and `maximumNumber`
- `minimum` and `minimumNumber`

In the arith dialect they are respectively named `maximumf` and
`maxnumf`, `minimumf` and `minnumf` so I use these names.

These operations only differ in how they handle NaN values. For
`maximumf` and `minimumf`, if any operand is NaN, then the result is
NaN, ie, NaN is propagated. For `maxnumf` and `minnumf`, if any operand
is NaN, then the other operand is returned, ie, NaN is absorbed. The
following identities hold:
```
maximumf(x, NaN) = maximumf(NaN, x) = NaN
maxnumf(x, NaN) = maxnumf(NaN, x) = x
```
(and same for min).

#### Arith folders

In the following I am talking about the folders for the arith
operations. The folders implement the following canonicalizations (`op`
is one of maximumf, maxnumf, minimumf, minnumf):
1. `op(x, x)` folds to `x` 
2. for `op(x, y)`, if `y` folds to the neutral element of the `op`, then
the `op` is folded to `x`.
    1. The neutral element of `maximumf` is -Infty
    2. The neutral element of `minimumf` is +Infty
3. The neutral element of `maxnumf` and `minnumf` is NaN as shown above.
3. for `op(x, y)`, if both `x` and `y` fold to constants `x'` and `y'`,
then the `op` is folded and the result is calculated with a
corresponding runtime function.

The folders are properly implemented for `maximumf` and `minimumf`, but
the same implementations were copied for the respective `maxnumf` and
`minnumf` functions. This means the neutral element of the second folder
above is wrong:
- `maxnumf(x, -Infty)` is folded to `x`, but that's wrong, because if
`x` is NaN then -Infty should be the result
- `minnumf(x, +Infty)` is folded to `x`, but same thing, the result
should be +Infty when `x` is NaN.

This is fixed by using `NaN` as neutral element for the `maxnumf` and
`minnumf` ops.[^1]

Again because of copy paste mistake, the third pattern above is using
`llvm::maximum` instead of `llvm::maximumnum` to calculate the result in
case both arguments fold to a constant:
- `maxnumf(NaN, x')` would have been folded to `llvm::maximum(NaN, x')`
which is `NaN`, whereas the result should be `x'`.

This folder for `minnumf` already correctly uses `llvm::minnum`, but I
fixed the one for `maxnumf` in this PR.


[^1]: this is by the way already correctly implemented in
[`arith::getIdentityValueAttr`](a821964e03/mlir/lib/Dialect/Arith/IR/ArithOps.cpp (L2493-L2498))
2024-11-27 21:06:49 +01:00
Ian Wood
06514c5501
[MLIR][Linalg] Fix linalg crash during elementwise op fusion (#117667)
`isOpOperandCanBeDroppedAfterFusedLinalgs` crashes when `indexingMaps`
is empty. This can occur when `producer` only has DPS init operands and
`consumer ` only has a single DPS input operand (all operands are
ignored and nothing gets added to `indexingMaps`). This is because
`concatAffineMaps` wasn't handling the maps being empty properly.


Similar to `canOpOperandsBeDroppedImpl`, I added an early return when
the maps are of size zero. Additionally, `concatAffineMaps`'s
declaration comment says it returns an empty map when `maps` is empty
but it has no way to get the `MLIRContext` needed to construct the empty
affine map when the array is empty. So, I changed this to take the
context.


__NOTE: concatAffineMaps now takes an MLIRContext to be able to
construct an empty map in the case where `maps` is empty.__

---------

Signed-off-by: Ian Wood <ianwood2024@u.northwestern.edu>
Co-authored-by: Quinn Dawkins <quinn.dawkins@gmail.com>
2024-11-26 16:00:18 -08:00
Christopher Bate
ced2fc7819
[mlir][bufferization] Fix OneShotBufferize when defaultMemorySpaceFn is used (#91524)
As described in issue llvm/llvm-project#91518, a previous PR
llvm/llvm-project#78484 introduced the `defaultMemorySpaceFn` into
bufferization options, allowing one to inform OneShotBufferize that it
should use a specified function to derive the memory space attribute
from the encoding attribute attached to tensor types.

However, introducing this feature exposed unhandled edge cases,
examples of which are introduced by this change in the new test under

`test/Dialect/Bufferization/Transforms/one-shot-bufferize-encodings.mlir`.

Fixing the inconsistencies introduced by `defaultMemorySpaceFn` is
pretty simple. This change:

- Updates the `bufferization.to_memref` and `bufferization.to_tensor`
  operations to explicitly include operand and destination types,
  whereas previously they relied on type inference to deduce the
  tensor types. Since the type inference cannot recover the correct
  tensor encoding/memory space, the operand and result types must be
  explicitly included. This is a small assembly format change, but it
  touches a large number of test files.

- Makes minor updates to other bufferization functions to handle the
  changes in building the above ops.

- Updates bufferization of `tensor.from_elements` to handle memory
  space.


Integration/upgrade guide:

In downstream projects, if you have tests or MLIR files that explicitly
use
`bufferization.to_tensor` or `bufferization.to_memref`, then update
them to the new assembly format as follows:

```
%1 = bufferization.to_memref %0 : memref<10xf32>
%2 = bufferization.to_tensor %1 : memref<10xf32>
```

becomes

```
%1 = bufferization.to_memref %0 : tensor<10xf32> to memref<10xf32>
%2 = bufferization.to_tensor %0 : memref<10xf32> to tensor<10xf32> 
```
2024-11-26 09:45:57 -07:00
7FM
619e4b7154
[MLIR][Arith] SelectOp fix invalid folding (#117555)
The pattern `select %x, true, false => %x` is only valid in case that
the return type is identical to the type of `%x` (i.e., i1). Hence, the
check `isInteger(1)` was replaced with `isSignlessInteger(1)`.

Fixes: https://github.com/llvm/llvm-project/issues/117554
2024-11-26 09:11:00 -05:00
Victor Perez
59b3630e03
[MLIR][SPIR-V] Drop commas from split barrier operations ASM format (#116673)
Drop commas from split barrier operations assembly format.

Signed-off-by: Victor Perez <victor.perez@codeplay.com>


Depends on #116648, review ec8d35471602cd88aa2ebaf239b698ef3ba353bd
only.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-11-26 15:08:31 +01:00
lorenzo chelini
4a7b56e6e7
[MLIR][Arith] Add denormal attribute to binary/unary operations (#112700)
Add support for denormal in the Arith dialect (binary and unary
operations).
Denormal are attached to every operation, and they can be of three
different
kinds:

1) ieee, denormal are preserved and processed as defined by IEEE 754
rules.

2) preserve sign, a mode where denormal numbers are flushed to zero, but
the
sign of the zero (+0 or -0) is preserved.

3) positive zero, a mode where all denormal numbers are flushed to
positive zero
(+0), ignoring the sign of the original number.

Denormal refers to both the operands and the result. Currently only
lowering for
ieee is supported.
2024-11-26 11:58:43 +01:00
Ivan Butygin
d471c85e65
[mlir][int-range] Update int range inference for arith.xori (#117272)
Previous impl was getting incorrect results for widths > i1 and was
disabled.

While same algorithm can be used for `andi` and `ori` too, without
additional modifications it will produce less precise result.
2024-11-26 13:50:43 +03:00
Andrzej Warzyński
1b2c8f104f
[mlir][linalg] Extract GeneralizePadOpPattern into a standalone transformation (#117329)
Currently, `GeneralizePadOpPattern` is grouped under
`populatePadOpVectorizationPatterns`. However, as noted in #111349, this
transformation "decomposes" rather than "vectorizes" `tensor.pad`. As
such, it functions as:
  * a vectorization _pre-processing_ transformation, not
  * a vectorization transformation itself.

To clarify its purpose, this PR turns `GeneralizePadOpPattern` into a
standalone transformation by:
  * introducing a dedicated `populateDecomposePadPatterns` method,
  * adding a `apply_patterns.linalg.decompose_pad` Transform Dialect Op,
  * removing it from `populatePadOpVectorizationPatterns`.

In addition, to better reflect its role, it is renamed as "decomposition"
rather then "generalization".  This is in line with the recent renaming
of similar ops, i.e. tensor.pack/tensor.unpack Ops in #116439.
2024-11-26 08:11:15 +00:00
Krzysztof Drewniak
ece4e1276e
[mlir][Affine] Split off delinearize parts that depend on last component (#117015)
If we have

    %0 = affine.linearize_index disjoint [%a, %b] by (A, B)
    %1:3 = affine.delinearize_index %0 into (A, B1, B2)

where B = B1 * B2 (or some mor complex product), we can simplify this to

    %0 = affine.linearize_index disjoint [%a] by (A)
    %1a:1 = affine.delinearize_index %0 into (A)
    %1b:2 = affine.delinearize_index %b into (B1, B2)

This, and more complex cases, prevent us from adding terms together only
to divide them away from each other.

---------

Co-authored-by: Abhishek Varma <abhvarma@amd.com>
2024-11-25 16:26:19 -06:00
Yadong Chen
a5506a39e0
[mlir][spirv] Use assemblyFormat to define {InBound}PtrAccessChainOp assembly (#116943)
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.

Changes:
updates the PtrAccessChainOp and InBoundPtrAccessChainOp defined in
SPIRVMemoryOps.td to use assemblyFormat. Removes part print/parse from
MemoryOps.cpp which is now generated by assemblyFormat
Updates tests to updated format

Issue: #73359
2024-11-25 10:11:07 -05:00
Oleksandr "Alex" Zinenko
5ce4d4c775
[mlir] fix memory effects in GPU barrier elimination (#117432)
Existing implementation may trigger infinite cycles when collecting
effects above or below the current block after wrapping around a
loop-like construct. Limit this case to only looking at the immediate
block (loop body). This is correct because wrap around is intended to
consider effects of different iterations of the same loop and shouldn't
be existing the loop block.

Reported-by: Fabian Mora <fmora.dev@gmail.com>
Co-authored-by: Fabian Mora <fmora.dev@gmail.com>
2024-11-24 23:25:11 +01:00
Uday Bondhugula
132de3a71f
[MLIR] Fix arbitrary checks in affine LICM (#116469)
Fix arbitrary checks and hardcoding/specialcasing  in affine LICM. Drop
unnecessary (too much) debug logging.

This pass is still unsound due to not handling aliases. This will have
to be handled later.
2024-11-23 07:07:56 +05:30
Uday Bondhugula
be750200ec
[MLIR] Fix unchecked use of memref memory space attr in affine data copy generate (#116763)
Fix unchecked use of memref memory space attr in affine data copy
generate. In the case of memory accesses without a memory space
attribute or those other than integer attributes, the pass treats them
as slow memory spaces.

Fixes https://github.com/llvm/llvm-project/issues/116536
2024-11-23 07:06:06 +05:30
Uday Bondhugula
b3909f4298
[MLIR] Drop assumption of a surrounding builtin.func in promoteIfSingleIteration (#116323)
Drop assumption of a surrounding builtin.func in
promoteIfSingleIteration.
Fixes https://github.com/llvm/llvm-project/issues/116042
2024-11-23 07:03:19 +05:30
Petr Kurapov
ecaf2c335c
[MLIR] Move warp_execute_on_lane_0 from vector to gpu (#116994)
Please see the related RFC here:
https://discourse.llvm.org/t/rfc-move-execute-on-lane-0-from-vector-to-gpu-dialect/82989.

This patch does exactly one thing - moves the op to gpu.
2024-11-22 15:30:47 +01:00
Krzysztof Drewniak
9e8200c718
[mlir][Affine] Expand affine.[de]linearize_index without affine maps (#116703)
As the documentation for -affine-expand-index-ops says,
affine.delinearize_index and affine.linearize_index don't need to be
expanded into the affine dialect.

Expanding these operations into affine.apply operations can introduce
unwanted "simplifications", mainly translations of `(dN mod C + ...)` to
`(dN + ... - (dN floordiv C) * C)` and similar, which create worse
generated code. This commit resolves this issue by expanding out
affine.delanierize_index directly.

In addition, the lowering of affine.linearize_index now sorts the
operands by loop-independence, allowing an increased amount of
loop-invariant code motion after lowering.

The old behavior is preserved as -expand-affine-index-ops-as-affine but
is no longer the default
2024-11-21 11:36:32 -06:00
Krzysztof Drewniak
0ac889b6b0
[mlir][Affine] Extend linearize/delinearize cancelation to partial tails (#116872)
xisting patterns would cancel out the linearize_index /
delinearize_index pairs that had the exact same basis, like

    %0 = affine.linearize_index [%w, %x, %y, %z] by (X, Y, Z) : index
    %1:4 = affine.delinearize_index %0 into (W, X, Y, Z) : index, ...

This commit extends the canonicalization to handle instances where the
entire basis doesn't match, as in

    %0 = affine.linearize_index [%w, %x, %y, %z] by (X, Y, Z) : index
    %1:3 = affine.delinearize_index %0 into (XY, Y, Z) : index, ...

where we can replace the last two results of the delinearize_index
operation with the last two inputs of the linearize_index, creating a
more canonical (fewer total computations to perform) result.
2024-11-21 11:36:08 -06:00
donald chen
dbe159b3f7
[mlir] [IR] Allow zero strides in StridedLayoutAttr (#116463)
Disabling memrefs with a stride of 0 was intended to prevent internal
aliasing, but this does not address all cases : internal aliasing can
still occur when the stride is less than the shape.

On the other hand, a stride of 0 can be very useful in certain
scenarios. For example, in architectures that support multi-dimensional
DMA, we can use memref::copy with a stride of 0 to achieve a broadcast
effect.

This commit removes the restriction that strides in memrefs cannot be 0.
2024-11-21 14:17:28 +08:00
Diego Caballero
32913724ac
[mlir][vector] Fix 0-d vector transfer mask inference (#116526)
When inferring the mask of a transfer operation that results in a single `i1` element, 
we could represent it using either `vector<i1>` or vector<1xi1>. To avoid type mismatches,
this PR updates the mask inference logic to consistently generate `vector<1xi1>` for
these cases. We can enable 0-D masks if they are needed in the future.

See: https://github.com/llvm/llvm-project/issues/116197
2024-11-20 20:57:39 -08:00
Matthias Springer
cbc7802233
[mlir][bufferization] Remove finalizing-bufferize pass (#114154)
The dialect conversion-based bufferization passes have been migrated to
One-Shot Bufferize about two years ago. To clean up the code base, this
commit removes the `finalizing-bufferize` pass, one of the few remaining
parts of the old infrastructure. Most bufferization passes have already
been removed.

Note for LLVM integration: If you depend on this pass, migrate to
One-Shot Bufferize or copy the pass to your codebase.

Depends on #114152.
2024-11-21 10:51:23 +09:00
Ivan Butygin
0733f38414
[mlir][int-range] Limit xor int range inference to i1 (#116968)
Fixes https://github.com/llvm/llvm-project/issues/82168

`intrange::inferXor` was incorrectly handling ranges for widths > i1
(see example in code). Limit it to i1 for now. For bigger widths it will
return maxRange.
2024-11-20 20:12:33 +03:00
Andrzej Warzyński
d33673ab05
[mlir][vector][nfc] Update test for mask elimination (#112130)
Updates one example so that:
  * it uses `vector.mask`,
  * upper loop bound is a multiple of the loop step,
  * use `vector.outerproduct` instead of "test.some_computation".

This makes this example a bit closer to realistic cases, which has
always been the goal for this test.
2024-11-20 08:04:16 +00:00
lialan
f981ee7efc
[MLIR] extend getCompressedMaskOp support in VectorEmulateNarrowType (#116122)
Previously when `numFrontPadElems` is not zero, `getCompressedMaskOp`
produces wrong result if the mask generator op is a
`vector.create_mask`.

This patch resolves the issue by including `numFrontPadElems` into the
mask generation.

Signed-off-by: Alan Li <me@alanli.org>
2024-11-19 16:49:05 -08:00
Matthias Springer
e394fecd5b
[mlir][func] Remove func-bufferize pass (#114152)
The dialect conversion-based bufferization passes have been migrated to
One-Shot Bufferize about two years ago. To clean up the code base, this
commit removes the `func-bufferize` pass, one of the few remaining parts
of the old infrastructure. Most bufferization passes have already been
removed.

Note for LLVM integration: If you depend on this pass, migrate to
One-Shot Bufferize or copy the pass to your codebase.
2024-11-20 09:29:26 +09:00
Kyle Wang
d8bd7f11c8
[mlir] Support ROCDL::ReadlaneOp (#116593)
Support ROCDL::ReadlaneOp to solve
https://github.com/ROCm/triton-internal/issues/411.
2024-11-19 17:36:30 -06:00
Yadong Chen
bdf00e2216
[mlir][spirv] Use assemblyFormat to define AccessChainOp assembly (#116545)
see #73359

Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out cpp interfaces.

Changes:
- updates the AccessChainOp defined in SPIRVMemoryOps.td to use
assemblyFormat.
- Removes part print/parse from MemoryOps.cpp which is now generated by
assemblyFormat
- Updates tests to updated format
2024-11-19 09:15:52 -05:00
Andrzej Warzyński
0775088234
[mlir] Rename GeneralizeOuterUnitDims{Un}PackOpPatterns (#116439)
Renames:
  * `GeneralizeOuterUnitDimsPackOpPattern`,
  * `GeneralizeOuterUnitDimsUnPackOpPattern`,

as
  * `DecomposeOuterUnitDimsPackOpPattern`,
  * `DecomposeOuterUnitDimsUnPackOpPattern`,

respectively. The new name better describes the underlying
transformation.
2024-11-19 09:09:33 +00:00
Ivan R. Ivanov
980d5fb2d0
[MLIR][omp] Add omp operations for OpenMP workshare (#101443)
Add the `omp.workshare` and `omp.workshare.loop_wrapper` operations used for the implementation of the `workshare` construct in flang.
2024-11-19 16:43:05 +09:00
lialan
6626ed6f9f
[MLIR] Fix BubbleDownVectorBitCastForExtract crash on non-static index (#116518)
Previously the patch was not expecting to handle non-static index, when
the index is a non constant value it will crash.
    
This patch is to make sure it return gracefully instead of crashing.
2024-11-18 17:25:12 -08:00
Krzysztof Drewniak
31aa7f34e0
[mlir][Affine] Let affine.[de]linearize_index omit outer bounds (#116103)
The affine.delinearize_index and affine.linearize_index operations, as
currently defined, require providing a length N basis to [de]linearize N
values. The first value in this basis is never used during lowering and
is unused during lowering. (Note that, even though it isn't used during
lowering it can still be used to, for example, remove length-1 outputs
from a delinearize).

This dead value makes sense in the original context of these operations,
which is linearizing or de-linearizing indexes to memref<>s, vector<>s,
and other shaped types, where that outer bound is avaliable and may be
useful for analysis.

However, other usecases exist where the outer bound is not known. For
example:

    %thread_id_x = gpu.thread_id x : index
%0:3 = affine.delinearize_index %thread_id_x into (4, 16) : index,index,
index

In this code, we don't know the upper bound of the thread ID, but we do
want to construct the ?x4x16 grid of delinearized values in order to
further partition the GPU threads.

In order to support such usecases, we broaden the definition of
affine.delinearize_index and affine.linearize_index to make the outer
bound optional.

In the case of affine.delinearize_index, where the number of results is
a function of the size of the passed-in basis, we augment all existing
builders with a `hasOuterBound` argument, which, for backwards
compatibilty and to preserve the natural usage of the op, defaults to
`true`. If this flag is true, the op returns one result per basis
element, if it is false, it returns one extra result in position 0.

We also update existing canonicalization patterns (and move one of them
into the folder) to handle these cases. Note that disagreements about
the outer bound now no longer prevent delinearize/linearize
cancelations.
2024-11-18 15:41:54 -06:00
Victor Perez
ad3b291879
[MLIR][SPIRV] Add definition for SPV_INTEL_split_barrier ops (#115738)
The [`SPV_INTEL_split_barrier`  extension](https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_split_barrier.html)
defines operations to split control barrier semantics in two operations.
Add support for these operations (arrive and wait) to the dialect.

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-11-18 12:08:54 +01:00
Kunwar Grover
2f925d75de
[mlir][Vector] Move insert/extractelement distribution patterns to insert/extract (#116425)
This is a NFC-ish change that moves
vector.extractelement/vector.insertelement vector distribution patterns
to vector.insert/vector.extract.

Before:

0-d/1-d vector.extract -> vector.extractelement -> distributed
vector.extractelement
2-d+ vector.extract -> distributed vector.extract

After:

scalar input vector.extract -> distributed vector.extract
vector.extractelement -> distributed vector.extract
2d+ vector.extract -> distributed vector.extract

The same changes are done for insertelement/insert. The change allows us
to remove reliance on vector.extractelement/vector.insertelement, which
are soon to be depreciated:
https://discourse.llvm.org/t/rfc-psa-remove-vector-extractelement-and-vector-insertelement-ops-in-favor-of-vector-extract-and-vector-insert-ops/71116/8

No extra tests are included because this patch doesn't introduce /
remove any functionality. It only changes the chain of lowerings. This
change can be completly NFC if we make the distributed operation
vector.extractelement/vector.insertelement, but that is slightly weird,
because you are going from extractelement -> extract -> extractelement.
2024-11-18 10:59:49 +00:00
Victor Perez
4f78f85190
[MLIR][SPIRV] Add definition and (de)serialization for cache controls (#115461)
[SPV_INTEL_cache_controls](https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.html)
defines decorations for load and store cache control. Add support for
this extension in the SPIR-V dialect.

As several `CacheControlLoadINTEL` and `CacheControlStoreINTEL` may be
applied to the same value, these are represented as array attributes.
(De)Serialization takes care of this representation.

---------

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2024-11-18 09:42:31 +01:00
Andrzej Warzyński
63b926af5f
[mlir] Add apply_patterns.linalg.generalize_pack_unpack TD Op (#116373)
This PR introduces populateGeneralizePatterns, which collects the
following patterns:

  * `GeneralizeOuterUnitDimsPackOpPattern`,
  * `GeneralizeOuterUnitDimsUnPackOpPattern` (currently a TODO).

These patterns are wrapped in a new Transform Dialect Op:
`apply_patterns.linalg.generalize_pack_unpack`. This Op facilitates
creating more involved end-to-end compilation pipelines for
`tensor.pack` and `tensor.unpack` operations. It will be required in an
upcoming PR building on top of #115698.

No new tests are added in this PR. Instead, existing tests from:

  * "generalize-tensor-pack.mlir"

are reused. To achieve this:

  * I've updated the test to use
    `transform.apply_patterns.linalg.generalize_pack_unpack` instead of
    the flag
    `--test-linalg-transform-patterns="test-generalize-tensor-pack"`,
    avoiding artificial tests solely for the TD Op.
  * The TD sequence is saved to a new file, "generalize_pack.mlir", and
    pre-loaded using the option:

`--transform-preload-library='transform-library-paths=%p/td/generalize_pack.mlir'`
    This avoids duplicating the sequence for every "split" in the input
    file.
  * Added "lit.local.cfg" to exclude the "test/Dialect/Linalg/td"
    directory from test discovery, ensuring "generalize_pack.mlir" is
    not treated as a test file.
2024-11-18 07:51:18 +00:00
agozillon
b5db75bfce
[OpenMP][MLIR] Descriptor explicit member map lowering changes (#113556)
This is one of 3 PRs in a PR stack that aims to add support for explicit
mapping of allocatable members in derived types.

The primary changes in this PR are the OpenMPToLLVMIRTranslation.cpp
changes, which are small and seek to alter the current member mapping to
add an additional map insertion for pointers. Effectively, if the member
is a pointer (currently indicated by having a varPtrPtr field) we add an
additional map for the pointer and then alter the subsequent mapping of
the member (the data) to utilise the member rather than the parents base
pointer. This appears to be necessary in certain cases when mapping
pointer data within record types to avoid segfaulting on device (due to
incorrect data mapping). In general this record type mapping may be
simplifiable in the future.

There are also additions of tests which should help to showcase the
affect of the changes above.
2024-11-16 12:26:29 +01:00
Kunwar Grover
db115ba3ef
[mlir][Linalg] Fix non-matmul linalg structured ops (#116412)
3ad0148020
broke linalg structured ops other than MatmulOp.

The patch:

- Changes the printer to hide additional attributes, which weren't
hidden before: "indexing_maps".
- Changes the build of every linalg structured op to have an indexing
map for matmul.

These changes combined, hide the problem until you print the operation
in it's generic form.

Reproducer:

```mlir
func.func public @bug(%arg0 : tensor<5x10x20xf32>, %arg1 : tensor<5x20x40xf32>, %arg3 : tensor<5x10x40xf32>) -> tensor<5x10x40xf32> {
  %out = linalg.batch_matmul ins(%arg0, %arg1 : tensor<5x10x20xf32>, tensor<5x20x40xf32>)
      outs(%arg3 : tensor<5x10x40xf32>) -> tensor<5x10x40xf32>
  func.return %out : tensor<5x10x40xf32>
}
```

Prints fine, with `mlir-opt <file>`, but if you do `mlir-opt
--mlir-print-op-generic <file>`:

```
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
#map3 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
#map4 = affine_map<(d0, d1, d2, d3) -> (d0, d3, d2)>
#map5 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2)>
"builtin.module"() ({
  "func.func"() <{function_type = (tensor<5x10x20xf32>, tensor<5x20x40xf32>, tensor<5x10x40xf32>) -> tensor<5x10x40xf32>, sym_name = "bug", sym_visibility = "public"}> ({
  ^bb0(%arg0: tensor<5x10x20xf32>, %arg1: tensor<5x20x40xf32>, %arg2: tensor<5x10x40xf32>):
    %0 = "linalg.batch_matmul"(%arg0, %arg1, %arg2) <{operandSegmentSizes = array<i32: 2, 1>}> ({
    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
      %1 = "arith.mulf"(%arg3, %arg4) <{fastmath = #arith.fastmath<none>}> : (f32, f32) -> f32
      %2 = "arith.addf"(%arg5, %1) <{fastmath = #arith.fastmath<none>}> : (f32, f32) -> f32
      "linalg.yield"(%2) : (f32) -> ()
    }) {indexing_maps = [#map, #map1, #map2], linalg.memoized_indexing_maps = [#map3, #map4, #map5]} : (tensor<5x10x20xf32>, tensor<5x20x40xf32>, tensor<5x10x40xf32>) -> tensor<5x10x40xf32>
    "func.return"(%0) : (tensor<5x10x40xf32>) -> ()
  }) : () -> ()
}) : () -> ()
```

The batch_matmul operation's builder now always inserts a indexing_map
which is unrelated to the operation itself. This was caught when a
transformation from one LinalgStructuredOp to another, tried to pass
it's attributes to the other ops builder and there were multiple
indexing_map attributes in the result.

This patch fixes this by specializing the builders for MatmulOp with
indexing map information.
2024-11-16 08:13:10 +00:00
lialan
ef92aba52a
[MLIR] Fix VectorEmulateNarrowType constant op mask bug (#116064)
This commit adds support for handling mask constants generated by the
`arith.constant` op in the `VectorEmulateNarrowType` pattern.
Previously, this pattern would not match due to the lack of mask
constant handling in `getCompressedMaskOp`.

The changes include:

1. Updating `getCompressedMaskOp` to recognize and handle
`arith.constant` ops as mask value sources.

2. Handling cases where the mask is not aligned with the emulated load
width. The compressed mask is adjusted to account for the offset.

Limitations:
- The arith.constant op can only have 1-dimensional constant values.

Resolves: #115742

Signed-off-by: Alan Li <me@alanli.org>
2024-11-15 10:06:40 -08:00
Krzysztof Drewniak
f2e42d9324
[mlir][IntRangeInference] Handle ceildivsi(INT_MIN, x > 1) as expected (#116284)
Fixes #115293

While the definition of ceildivsi is integer division, rounding up, most
implementations will use `-(-a / b)` for dividing `a ceildiv b` with `a`
negative and `b` positive.

Mathematically, and for most integers, these two definitions are
equivalent. However, with `a == INT_MIN`, the initial negation is a
noop, which means that, while divinding and rounding up would give a
negative result, `-((- INT_MIN) / b)` is `-(INT_MIN / b)`, which is
positive.

This commit adds a special case to ceilDivSI inference to handle this
case and bring it in line with the operational instead of the
mathematical semantics of ceiling division.
2024-11-15 11:43:05 -06:00