This seems to be an issue common to both GCC and LLVM. There are various
RISC-V FCVT instructions where the frm field makes no difference to the
output as the result is always exact (e.g. fcvt.d.s, fcvt.s.h,
fcvt.d.h). As with GCC, we always generate a form of these fcvt
instructions where frm=0b000. However, the ISA manual _doesn't_ state
that frm values are invalid, and we should ensure we can accept them.
This patch does so by adding the frm field to fcvt.d.s and adding an
InstAlias so that if no frm is specified, it defaults to rne (0b000).
This patch just corrects fcvt.d.s in order to allow the approach to be
reviewed, before applying it to the other affected instructions.
I haven't added tests to llvm/test/MC/Disassembler/RISCV, because it
doesn't seem necessary to test there in addition to our usual round-trip
tests in llvm/test/MC/RISCV. But feedback is welcome.
Recently added tests ensure that the default `rne` rounding mode is
printed as desired.
This finishes the work of replacing OperandMatchResultTy with
ParseStatus, started in D154101.
As a drive-by change, rename some RegNo variables to just Reg
(a leftover from the days when RegNo had 'unsigned' type).
According to `riscv-v-spec-1.0.pdf` page 52:
> masked va >= x, vd == v0
> pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
> expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
The resulting `vmslt{u}.vx` is not masked. This patch fixes the logic in `RISCVAsmParser`, to make the behavior consistent with the case "masked va >= x, any vd" in the later part of the code, where no mask op is added.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D158392
For the most part, MC version of vector instructions don't model when
the destination is also a source. This primarily occurs for mask/tail
undisturbed. The MC layer can't see the policy bits so this kind of
makes sense.
We also lumped FMA instructions into this, but the destination of
FMA is an arithmetic source not just an undisturbed value. This needs
to be correct for llvm-mca to understand the dependency for the FMA
instructions. Though every other instruction is still wrong for
tail/mask undisturbed.
This patch models the FMA instructions correctly at the MCA layer.
This necessitates changes to the assembler to offset operand numbers.
I've added the extra sched class operand and fixed the operand order
for the scalar read class.
Reviewed By: rogfer01
Differential Revision: https://reviews.llvm.org/D151850
Since the spec doesn't describe these behaviors as invalid,
the llvm-mc should just make them take care by hardware.
Differential Revision: https://reviews.llvm.org/D155669
Support for below CSRs is addeed -
1. Branch Prediction Mode CSR
2. Feature Disable CSR
3. Power Dial CSR
4. RNMI CSRs
spec:https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
This patch removes AltName field from SysReg class because we are now using
separate class for custom vendor CSRs. Also, all use of AltName have been changed
to DeprecatedName because both were interchangeably used for old names which are
not in use in latest RISCV spec.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153499
We were checking that the encoding within our internal list of
registers was even. This worked today because X0 happens to have
an even value in that enum. This can break if any registers are
added before X0.
The correct check is to make sure it has an even offset from X0.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D155104
This implements the v1.0-rc1 draft extension.
amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must
be even registers. I've opted to implement this restriction in
RISCVAsmParser::validateInstruction even though for codegen we'll need a
new register class and can then remove this validation. This also
sidesteps, for now, the issue of amocas.d being different on rv32 vs
rv64.
See <https://github.com/riscv-non-isa/riscv-c-api-doc/issues/37> for the
issue of needing an agreed asm register constraint for register pairs.
Differential Revision: https://reviews.llvm.org/D149248
ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return Error(L, "msg");
```
when with MatchOperandResultTy it had to be:
```
Error(L, "msg");
return MatchOperand_ParseFail;
```
It also has more appropriate name since parse* methods are not only for
parsing operands.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D154291
In preparation for removing the `#include "llvm/ADT/StringExtras.h"`
from the header to source file of `llvm/Support/Error.h`, first add in
all the missing includes that were previously included transitively
through this header.
Otherwise subsequent .option arch, +foo directives (but not -, since
those have their own separate validation) fail the parseFeatureBits
check, leading to cascading errors.
Reviewed By: luismarques, MaskRay
Differential Revision: https://reviews.llvm.org/D152273
The current interface requires some rather ugly tracking of state due to
splitting up the calls for each argument. Instead, pack them all into a
single call by passing an ArrayRef. Also clean up the dodgy whitespace
emitted for the directive whilst here; there was a stray space between
the tab and .option, and there was a tab rather than a space after the
first comma for some strange reason.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152193
Currently the early-return flow in the infinite loop makes it hard to
find the non-error termination points amongst the sea of errors. Rewrite
it with a more conventional control flow that has a clear loop guard (in
place of one of the early returns) and a break (in place of the other),
and with greater code reuse.
This has a small effect on the errors given for malformed input, as seen
in the affected test, and is probably more helpful as a result. Note
that we also bail early now if parseComma fails, as is standard.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D152192
This mirrors lla and is always GOT-relative, allowing an explicit
request to use the GOT without having to expand the instruction. This
then means la is just defined in terms of lla and lga in the assembler,
based on whether PIC is enabled, and at the codegen level we replace la
entirely with lga since we only ever use la there when we want to load
from the GOT (and assert that to be the case).
See https://github.com/riscv-non-isa/riscv-asm-manual/issues/50
Reviewed By: asb, MaskRay
Differential Revision: https://reviews.llvm.org/D107278
Probably going to do some other refactors after this, but this one
was easy and clearly reduces duplicate code.
Reviewed By: StephenFan
Differential Revision: https://reviews.llvm.org/D151771
Previously we lexed into a SmallVector and unlexed the tokens if
the parsing failed.
This patch gets rid of the SmallVector and the unlexing.
If the first token fails to parse, return MatchFail. This allows us
to fallback to parsing as an immediate. If we successfully parsed the
first token, use ParseFail if any later tokens fail to parse. This
avoids needing to UnLex the tokens.
I've used a state machine to keep track of what component we've
parsed so far.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D150753
This patch lets the assembler accept code like the following:
.Lbuf: ...
.set .Lbuf_len, . - .Lbuf
li a0, .Lbuf_len
It works by translating such instances of LI into an ADDI and inserting
the correct constant value via a new fixup.
Note that this means that the constant value is restricted to 12 bits
since we cannot insert new instructions during the relaxation stage.
Binutils seems to have the same restriction though.
This patch also fixes a small issue where the SMLoc of an LI wasn't
propagated when translated to ADDI. While this is technically unrelated
to the main functionality of this patch, it improves error messages
related to the new use of LI.
This patch does _not_ allow I-type instructions to take such symbolic
constants as well. While technically possible (and allowed by binutils),
it's probably better to implement this in another patch.
Fixes#57461
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D135960
This previously returned a bool to indicate success or failure and
returns a register through an output parameter.
Some callers used the bool to check for success. Some callers checked
for RISCV::NoRegister.
To make everything uniform, return the MCRegister directly and update
all callers to use MCRegister::isValid().
Reviewed By: barannikov88
Differential Revision: https://reviews.llvm.org/D150049
This patch add the instructions of zcmp extension.
Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions
co-author: @Scott Egerton, @ZirconLiu, @Lukacma, @Heda Chen, @luxufan, @heyiliang, @liaochunyu
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D132819
Have the ErrorInfo version call it after looking up ErrorInfo in
the Operands.
Use the new function in a few places that don't have ErrorInfo and
were also generating out of range messages.
This adds an option to emit the command line -mattr/-march into the
attributes of an object file. This can be useful to get objdump to
disassemble instructions that aren't in the base without forcing
users to add a .attribute to the assembly file.
The binutils assembler does this by default.
Similar option exists for ARM. I will wire it to a clang option in
another patch. Similar to https://reviews.llvm.org/D31813
Reviewed By: asb, kito-cheng
Differential Revision: https://reviews.llvm.org/D148782
Fold the 3 flag defines into the enum that defines TSFlags. Then
we don't have to extract them we can just test the bits directly
in TSFlags.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D148765
Even for experimental extensions, I think we always include "Std"
in the feature name.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146997
I think the failure was caused by a mistake in an earlier patch.
Original commit message:
We've supported .insn for non-compressed for a while. This finishes the compressed supported.
Differential Revision: https://reviews.llvm.org/D146663
Original commit message:
I recently added a check to make sure the lower 2 bits of the opcode
were 0x3. A post commit comment pointed out this would be allowed
for a custom extension when C is not supported.
Note, binutils does have this restriction.
We've supported .insn for non-compressed for a while. This finishes the compressed supported.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146663
The fake register class interferes too much with the autogenerated
register class tables. Especially the fake spill size.
I'm working on .insn support for compressed instructions and adding
AnyRegC broke CodeGen.
The lower 2 bits of the opcode must be 0x3. If the lower 2 bits are
0-2, it's a compressed instruction.
Merge 3 slightly different error messages into 1 to reduce code. The
messages differed slightly depending on whether we parsed a string
or an expression. The message gets a little more generic, but is no
more generic than what binutils prints.
