; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -vplan-print-after="printFinalVPlan$" -disable-output %s 2>&1 | FileCheck %s

define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-LABEL: VPlan for loop in 'switch4_default_common_dest_with_case'
; CHECK:  VPlan 'Final VPlan for VF={2},UF={1}' {
; CHECK-NEXT:  Live-in ir<%0> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<entry>:
; CHECK-NEXT:    IR   %start2 = ptrtoint ptr %start to i64
; CHECK-NEXT:    IR   %end1 = ptrtoint ptr %end to i64
; CHECK-NEXT:    IR   %0 = sub i64 %end1, %start2
; CHECK-NEXT:    EMIT vp<%min.iters.check> = icmp ult ir<%0>, ir<2>
; CHECK-NEXT:    EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT:  vector.ph:
; CHECK-NEXT:    EMIT vp<%n.mod.vf> = urem ir<%0>, ir<2>
; CHECK-NEXT:    EMIT vp<%n.vec> = sub ir<%0>, vp<%n.mod.vf>
; CHECK-NEXT:    vp<[[VP3:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<%n.vec> * ir<1>
; CHECK-NEXT:  Successor(s): vector.body
; CHECK-EMPTY:
; CHECK-NEXT:  vector.body:
; CHECK-NEXT:    EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, pred.store.continue ]
; CHECK-NEXT:    vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<%index>, ir<1>, ir<2>, ir<1>
; CHECK-NEXT:    EMIT vp<%next.gep> = ptradd ir<%start>, vp<%index>
; CHECK-NEXT:    EMIT vp<%next.gep>.1 = ptradd ir<%start>, vp<[[VP4]]>
; CHECK-NEXT:    WIDEN ir<%l> = load vp<%next.gep>
; CHECK-NEXT:    EMIT vp<[[VP5:%[0-9]+]]> = icmp eq ir<%l>, ir<-12>
; CHECK-NEXT:    EMIT vp<[[VP6:%[0-9]+]]> = icmp eq ir<%l>, ir<13>
; CHECK-NEXT:    EMIT vp<[[VP7:%[0-9]+]]> = or vp<[[VP5]]>, vp<[[VP6]]>
; CHECK-NEXT:    EMIT vp<[[VP8:%[0-9]+]]> = not vp<[[VP7]]>
; CHECK-NEXT:    EMIT vp<[[VP9:%[0-9]+]]> = extractelement vp<[[VP6]]>, ir<0>
; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP9]]>
; CHECK-NEXT:  Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.if:
; CHECK-NEXT:    CLONE store ir<0>, vp<%next.gep>
; CHECK-NEXT:  Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.continue:
; CHECK-NEXT:    EMIT vp<[[VP11:%[0-9]+]]> = extractelement vp<[[VP6]]>, ir<1>
; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP11]]>
; CHECK-NEXT:  Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.if:
; CHECK-NEXT:    CLONE store ir<0>, vp<%next.gep>.1
; CHECK-NEXT:  Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.continue:
; CHECK-NEXT:    EMIT vp<[[VP13:%[0-9]+]]> = extractelement vp<[[VP5]]>, ir<0>
; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP13]]>
; CHECK-NEXT:  Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.if:
; CHECK-NEXT:    CLONE store ir<42>, vp<%next.gep>
; CHECK-NEXT:  Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.continue:
; CHECK-NEXT:    EMIT vp<[[VP15:%[0-9]+]]> = extractelement vp<[[VP5]]>, ir<1>
; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP15]]>
; CHECK-NEXT:  Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.if:
; CHECK-NEXT:    CLONE store ir<42>, vp<%next.gep>.1
; CHECK-NEXT:  Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.continue:
; CHECK-NEXT:    EMIT vp<[[VP17:%[0-9]+]]> = extractelement vp<[[VP8]]>, ir<0>
; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP17]]>
; CHECK-NEXT:  Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.if:
; CHECK-NEXT:    CLONE store ir<2>, vp<%next.gep>
; CHECK-NEXT:  Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.continue:
; CHECK-NEXT:    EMIT vp<[[VP19:%[0-9]+]]> = extractelement vp<[[VP8]]>, ir<1>
; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP19]]>
; CHECK-NEXT:  Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.if:
; CHECK-NEXT:    CLONE store ir<2>, vp<%next.gep>.1
; CHECK-NEXT:  Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT:  pred.store.continue:
; CHECK-NEXT:    EMIT vp<%index.next> = add nuw vp<%index>, ir<2>
; CHECK-NEXT:    EMIT vp<[[VP21:%[0-9]+]]> = icmp eq vp<%index.next>, vp<%n.vec>
; CHECK-NEXT:    EMIT branch-on-cond vp<[[VP21]]>
; CHECK-NEXT:  Successor(s): middle.block, vector.body
; CHECK-EMPTY:
; CHECK-NEXT:  middle.block:
; CHECK-NEXT:    EMIT vp<%cmp.n> = icmp eq ir<%0>, vp<%n.vec>
; CHECK-NEXT:    EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT:  Successor(s): ir-bb<exit>, ir-bb<scalar.ph>
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<exit>:
; CHECK-NEXT:  No successors
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<scalar.ph>:
; CHECK-NEXT:    EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP3]]>, middle.block ], [ ir<%start>, ir-bb<entry> ]
; CHECK-NEXT:  Successor(s): ir-bb<loop.header>
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<loop.header>:
; CHECK-NEXT:    IR   %ptr.iv = phi ptr [ %start, %scalar.ph ], [ %ptr.iv.next, %loop.latch ] (extra operand: vp<%bc.resume.val> from ir-bb<scalar.ph>)
; CHECK-NEXT:    IR   %l = load i8, ptr %ptr.iv, align 1
; CHECK-NEXT:  No successors
; CHECK-NEXT:  }
;
entry:
  br label %loop.header

loop.header:
  %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
  %l = load i8, ptr %ptr.iv, align 1
  switch i8 %l, label %default [
  i8 -12, label %if.then.1
  i8 13, label %if.then.2
  i8 0, label %default
  ]

if.then.1:
  store i8 42, ptr %ptr.iv, align 1
  br label %loop.latch

if.then.2:
  store i8 0, ptr %ptr.iv, align 1
  br label %loop.latch

default:
  store i8 2, ptr %ptr.iv, align 1
  br label %loop.latch

loop.latch:
  %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 1
  %ec = icmp eq ptr %ptr.iv.next, %end
  br i1 %ec, label %exit, label %loop.header

exit:
  ret void
}