// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 6
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown \
// RUN: -emit-llvm %s -o - | FileCheck %s

// expected-no-diagnostics

// CHECK-LABEL: define internal void @_Z17triangular_loop_1v.omp_outlined(
// CHECK-SAME: ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK-NEXT:  [[ENTRY:.*:]]
// CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP1:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP2:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MIN:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MAX:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTMIN_LESS_MAX:%.*]] = alloca i8, align 1
// CHECK-NEXT:    [[DOTLOWER:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MIN4:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MAX7:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTMIN_LESS_MAX13:%.*]] = alloca i8, align 1
// CHECK-NEXT:    [[DOTLOWER16:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[K:%.*]] = alloca i32, align 4
// CHECK-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-NEXT:    store i32 0, ptr [[TMP]], align 4
// CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP0]], 1
// CHECK-NEXT:    store i32 [[ADD]], ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    store i32 9, ptr [[TMP]], align 4
// CHECK-NEXT:    [[TMP100:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD3:%.*]] = add i32 [[TMP100]], 1
// CHECK-NEXT:    store i32 [[ADD3]], ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP2]], [[TMP3]]
// CHECK-NEXT:    [[STOREDV:%.*]] = zext i1 [[CMP]] to i8
// CHECK-NEXT:    store i8 [[STOREDV]], ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK-NEXT:    br i1 [[LOADEDV]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]]
// CHECK:       [[COND_TRUE]]:
// CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    br label %[[COND_END:.*]]
// CHECK:       [[COND_FALSE]]:
// CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    br label %[[COND_END]]
// CHECK:       [[COND_END]]:
// CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP5]], %[[COND_TRUE]] ], [ [[TMP6]], %[[COND_FALSE]] ]
// CHECK-NEXT:    store i32 [[COND]], ptr [[TMP]], align 4
// CHECK-NEXT:    store i32 [[COND]], ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD5:%.*]] = add i32 [[TMP7]], 1
// CHECK-NEXT:    store i32 [[ADD5]], ptr [[TMP1]], align 4
// CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 1
// CHECK-NEXT:    store i32 [[ADD6]], ptr [[DOTLB_MIN4]], align 4
// CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], 1
// CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD9:%.*]] = add i32 [[TMP10]], 1
// CHECK-NEXT:    [[SUB:%.*]] = sub i32 10, [[ADD9]]
// CHECK-NEXT:    [[SUB10:%.*]] = sub i32 [[SUB]], 1
// CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[SUB10]], 1
// CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[DIV]], 1
// CHECK-NEXT:    [[ADD11:%.*]] = add i32 [[ADD8]], [[MUL]]
// CHECK-NEXT:    store i32 [[ADD11]], ptr [[TMP1]], align 4
// CHECK-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[ADD12:%.*]] = add i32 [[TMP11]], 1
// CHECK-NEXT:    store i32 [[ADD12]], ptr [[DOTLB_MAX7]], align 4
// CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTLB_MIN4]], align 4
// CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLB_MAX7]], align 4
// CHECK-NEXT:    [[CMP14:%.*]] = icmp ult i32 [[TMP12]], [[TMP13]]
// CHECK-NEXT:    [[STOREDV15:%.*]] = zext i1 [[CMP14]] to i8
// CHECK-NEXT:    store i8 [[STOREDV15]], ptr [[DOTMIN_LESS_MAX13]], align 1
// CHECK-NEXT:    [[TMP14:%.*]] = load i8, ptr [[DOTMIN_LESS_MAX13]], align 1
// CHECK-NEXT:    [[LOADEDV17:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK-NEXT:    br i1 [[LOADEDV17]], label %[[COND_TRUE18:.*]], label %[[COND_FALSE19:.*]]
// CHECK:       [[COND_TRUE18]]:
// CHECK-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTLB_MIN4]], align 4
// CHECK-NEXT:    br label %[[COND_END20:.*]]
// CHECK:       [[COND_FALSE19]]:
// CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTLB_MAX7]], align 4
// CHECK-NEXT:    br label %[[COND_END20]]
// CHECK:       [[COND_END20]]:
// CHECK-NEXT:    [[COND21:%.*]] = phi i32 [ [[TMP15]], %[[COND_TRUE18]] ], [ [[TMP16]], %[[COND_FALSE19]] ]
// CHECK-NEXT:    store i32 [[COND21]], ptr [[TMP1]], align 4
// CHECK-NEXT:    store i32 [[COND21]], ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB22:%.*]] = sub i32 10, [[TMP17]]
// CHECK-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
// CHECK-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
// CHECK-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
// CHECK-NEXT:    [[CONV:%.*]] = zext i32 [[DIV25]] to i64
// CHECK-NEXT:    [[MUL26:%.*]] = mul nsw i64 10, [[CONV]]
// CHECK-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB27:%.*]] = sub i32 10, [[TMP18]]
// CHECK-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
// CHECK-NEXT:    [[CONV29:%.*]] = zext i32 [[ADD28]] to i64
// CHECK-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[MUL26]], [[CONV29]]
// CHECK-NEXT:    [[SUB31:%.*]] = sub nsw i64 [[MUL30]], 1
// CHECK-NEXT:    store i64 [[SUB31]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP21]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    [[CMP32:%.*]] = icmp sgt i64 [[TMP22]], [[TMP23]]
// CHECK-NEXT:    br i1 [[CMP32]], label %[[COND_TRUE33:.*]], label %[[COND_FALSE34:.*]]
// CHECK:       [[COND_TRUE33]]:
// CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    br label %[[COND_END35:.*]]
// CHECK:       [[COND_FALSE34]]:
// CHECK-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    br label %[[COND_END35]]
// CHECK:       [[COND_END35]]:
// CHECK-NEXT:    [[COND36:%.*]] = phi i64 [ [[TMP24]], %[[COND_TRUE33]] ], [ [[TMP25]], %[[COND_FALSE34]] ]
// CHECK-NEXT:    store i64 [[COND36]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    store i64 [[TMP26]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND:.*]]
// CHECK:       [[OMP_INNER_FOR_COND]]:
// CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP28:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[CMP37:%.*]] = icmp sle i64 [[TMP27]], [[TMP28]]
// CHECK-NEXT:    br i1 [[CMP37]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]]
// CHECK:       [[OMP_INNER_FOR_BODY]]:
// CHECK-NEXT:    [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB38:%.*]] = sub i32 10, [[TMP30]]
// CHECK-NEXT:    [[SUB39:%.*]] = sub i32 [[SUB38]], 1
// CHECK-NEXT:    [[ADD40:%.*]] = add i32 [[SUB39]], 1
// CHECK-NEXT:    [[DIV41:%.*]] = udiv i32 [[ADD40]], 1
// CHECK-NEXT:    [[MUL42:%.*]] = mul i32 1, [[DIV41]]
// CHECK-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB43:%.*]] = sub i32 10, [[TMP31]]
// CHECK-NEXT:    [[ADD44:%.*]] = add i32 [[SUB43]], 1
// CHECK-NEXT:    [[MUL45:%.*]] = mul i32 [[MUL42]], [[ADD44]]
// CHECK-NEXT:    [[CONV46:%.*]] = zext i32 [[MUL45]] to i64
// CHECK-NEXT:    [[DIV47:%.*]] = sdiv i64 [[TMP29]], [[CONV46]]
// CHECK-NEXT:    [[MUL48:%.*]] = mul nsw i64 [[DIV47]], 1
// CHECK-NEXT:    [[ADD49:%.*]] = add nsw i64 0, [[MUL48]]
// CHECK-NEXT:    [[CONV50:%.*]] = trunc i64 [[ADD49]] to i32
// CHECK-NEXT:    store i32 [[CONV50]], ptr [[I]], align 4
// CHECK-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I]], align 4
// CHECK-NEXT:    [[ADD51:%.*]] = add i32 [[TMP32]], 1
// CHECK-NEXT:    [[CONV52:%.*]] = zext i32 [[ADD51]] to i64
// CHECK-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB53:%.*]] = sub i32 10, [[TMP35]]
// CHECK-NEXT:    [[SUB54:%.*]] = sub i32 [[SUB53]], 1
// CHECK-NEXT:    [[ADD55:%.*]] = add i32 [[SUB54]], 1
// CHECK-NEXT:    [[DIV56:%.*]] = udiv i32 [[ADD55]], 1
// CHECK-NEXT:    [[MUL57:%.*]] = mul i32 1, [[DIV56]]
// CHECK-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB58:%.*]] = sub i32 10, [[TMP36]]
// CHECK-NEXT:    [[ADD59:%.*]] = add i32 [[SUB58]], 1
// CHECK-NEXT:    [[MUL60:%.*]] = mul i32 [[MUL57]], [[ADD59]]
// CHECK-NEXT:    [[CONV61:%.*]] = zext i32 [[MUL60]] to i64
// CHECK-NEXT:    [[DIV62:%.*]] = sdiv i64 [[TMP34]], [[CONV61]]
// CHECK-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB63:%.*]] = sub i32 10, [[TMP37]]
// CHECK-NEXT:    [[SUB64:%.*]] = sub i32 [[SUB63]], 1
// CHECK-NEXT:    [[ADD65:%.*]] = add i32 [[SUB64]], 1
// CHECK-NEXT:    [[DIV66:%.*]] = udiv i32 [[ADD65]], 1
// CHECK-NEXT:    [[MUL67:%.*]] = mul i32 1, [[DIV66]]
// CHECK-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB68:%.*]] = sub i32 10, [[TMP38]]
// CHECK-NEXT:    [[ADD69:%.*]] = add i32 [[SUB68]], 1
// CHECK-NEXT:    [[MUL70:%.*]] = mul i32 [[MUL67]], [[ADD69]]
// CHECK-NEXT:    [[CONV71:%.*]] = zext i32 [[MUL70]] to i64
// CHECK-NEXT:    [[MUL72:%.*]] = mul nsw i64 [[DIV62]], [[CONV71]]
// CHECK-NEXT:    [[SUB73:%.*]] = sub nsw i64 [[TMP33]], [[MUL72]]
// CHECK-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB74:%.*]] = sub i32 10, [[TMP39]]
// CHECK-NEXT:    [[ADD75:%.*]] = add i32 [[SUB74]], 1
// CHECK-NEXT:    [[MUL76:%.*]] = mul i32 1, [[ADD75]]
// CHECK-NEXT:    [[CONV77:%.*]] = zext i32 [[MUL76]] to i64
// CHECK-NEXT:    [[DIV78:%.*]] = sdiv i64 [[SUB73]], [[CONV77]]
// CHECK-NEXT:    [[MUL79:%.*]] = mul nsw i64 [[DIV78]], 1
// CHECK-NEXT:    [[ADD80:%.*]] = add nsw i64 [[CONV52]], [[MUL79]]
// CHECK-NEXT:    [[CONV81:%.*]] = trunc i64 [[ADD80]] to i32
// CHECK-NEXT:    store i32 [[CONV81]], ptr [[J]], align 4
// CHECK-NEXT:    [[TMP40:%.*]] = load i32, ptr [[J]], align 4
// CHECK-NEXT:    [[ADD82:%.*]] = add i32 [[TMP40]], 1
// CHECK-NEXT:    [[CONV83:%.*]] = zext i32 [[ADD82]] to i64
// CHECK-NEXT:    [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB84:%.*]] = sub i32 10, [[TMP43]]
// CHECK-NEXT:    [[SUB85:%.*]] = sub i32 [[SUB84]], 1
// CHECK-NEXT:    [[ADD86:%.*]] = add i32 [[SUB85]], 1
// CHECK-NEXT:    [[DIV87:%.*]] = udiv i32 [[ADD86]], 1
// CHECK-NEXT:    [[MUL88:%.*]] = mul i32 1, [[DIV87]]
// CHECK-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB89:%.*]] = sub i32 10, [[TMP44]]
// CHECK-NEXT:    [[ADD90:%.*]] = add i32 [[SUB89]], 1
// CHECK-NEXT:    [[MUL91:%.*]] = mul i32 [[MUL88]], [[ADD90]]
// CHECK-NEXT:    [[CONV92:%.*]] = zext i32 [[MUL91]] to i64
// CHECK-NEXT:    [[DIV93:%.*]] = sdiv i64 [[TMP42]], [[CONV92]]
// CHECK-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB94:%.*]] = sub i32 10, [[TMP45]]
// CHECK-NEXT:    [[SUB95:%.*]] = sub i32 [[SUB94]], 1
// CHECK-NEXT:    [[ADD96:%.*]] = add i32 [[SUB95]], 1
// CHECK-NEXT:    [[DIV97:%.*]] = udiv i32 [[ADD96]], 1
// CHECK-NEXT:    [[MUL98:%.*]] = mul i32 1, [[DIV97]]
// CHECK-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB99:%.*]] = sub i32 10, [[TMP46]]
// CHECK-NEXT:    [[ADD100:%.*]] = add i32 [[SUB99]], 1
// CHECK-NEXT:    [[MUL101:%.*]] = mul i32 [[MUL98]], [[ADD100]]
// CHECK-NEXT:    [[CONV102:%.*]] = zext i32 [[MUL101]] to i64
// CHECK-NEXT:    [[MUL103:%.*]] = mul nsw i64 [[DIV93]], [[CONV102]]
// CHECK-NEXT:    [[SUB104:%.*]] = sub nsw i64 [[TMP41]], [[MUL103]]
// CHECK-NEXT:    [[TMP47:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP49:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB105:%.*]] = sub i32 10, [[TMP49]]
// CHECK-NEXT:    [[SUB106:%.*]] = sub i32 [[SUB105]], 1
// CHECK-NEXT:    [[ADD107:%.*]] = add i32 [[SUB106]], 1
// CHECK-NEXT:    [[DIV108:%.*]] = udiv i32 [[ADD107]], 1
// CHECK-NEXT:    [[MUL109:%.*]] = mul i32 1, [[DIV108]]
// CHECK-NEXT:    [[TMP50:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB110:%.*]] = sub i32 10, [[TMP50]]
// CHECK-NEXT:    [[ADD111:%.*]] = add i32 [[SUB110]], 1
// CHECK-NEXT:    [[MUL112:%.*]] = mul i32 [[MUL109]], [[ADD111]]
// CHECK-NEXT:    [[CONV113:%.*]] = zext i32 [[MUL112]] to i64
// CHECK-NEXT:    [[DIV114:%.*]] = sdiv i64 [[TMP48]], [[CONV113]]
// CHECK-NEXT:    [[TMP51:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB115:%.*]] = sub i32 10, [[TMP51]]
// CHECK-NEXT:    [[SUB116:%.*]] = sub i32 [[SUB115]], 1
// CHECK-NEXT:    [[ADD117:%.*]] = add i32 [[SUB116]], 1
// CHECK-NEXT:    [[DIV118:%.*]] = udiv i32 [[ADD117]], 1
// CHECK-NEXT:    [[MUL119:%.*]] = mul i32 1, [[DIV118]]
// CHECK-NEXT:    [[TMP52:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB120:%.*]] = sub i32 10, [[TMP52]]
// CHECK-NEXT:    [[ADD121:%.*]] = add i32 [[SUB120]], 1
// CHECK-NEXT:    [[MUL122:%.*]] = mul i32 [[MUL119]], [[ADD121]]
// CHECK-NEXT:    [[CONV123:%.*]] = zext i32 [[MUL122]] to i64
// CHECK-NEXT:    [[MUL124:%.*]] = mul nsw i64 [[DIV114]], [[CONV123]]
// CHECK-NEXT:    [[SUB125:%.*]] = sub nsw i64 [[TMP47]], [[MUL124]]
// CHECK-NEXT:    [[TMP53:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB126:%.*]] = sub i32 10, [[TMP53]]
// CHECK-NEXT:    [[ADD127:%.*]] = add i32 [[SUB126]], 1
// CHECK-NEXT:    [[MUL128:%.*]] = mul i32 1, [[ADD127]]
// CHECK-NEXT:    [[CONV129:%.*]] = zext i32 [[MUL128]] to i64
// CHECK-NEXT:    [[DIV130:%.*]] = sdiv i64 [[SUB125]], [[CONV129]]
// CHECK-NEXT:    [[TMP54:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB131:%.*]] = sub i32 10, [[TMP54]]
// CHECK-NEXT:    [[ADD132:%.*]] = add i32 [[SUB131]], 1
// CHECK-NEXT:    [[MUL133:%.*]] = mul i32 1, [[ADD132]]
// CHECK-NEXT:    [[CONV134:%.*]] = zext i32 [[MUL133]] to i64
// CHECK-NEXT:    [[MUL135:%.*]] = mul nsw i64 [[DIV130]], [[CONV134]]
// CHECK-NEXT:    [[SUB136:%.*]] = sub nsw i64 [[SUB104]], [[MUL135]]
// CHECK-NEXT:    [[MUL137:%.*]] = mul nsw i64 [[SUB136]], 1
// CHECK-NEXT:    [[ADD138:%.*]] = add nsw i64 [[CONV83]], [[MUL137]]
// CHECK-NEXT:    [[CONV139:%.*]] = trunc i64 [[ADD138]] to i32
// CHECK-NEXT:    store i32 [[CONV139]], ptr [[K]], align 4
// CHECK-NEXT:    [[TMP55:%.*]] = load i32, ptr [[J]], align 4
// CHECK-NEXT:    [[CMP140:%.*]] = icmp ult i32 [[TMP55]], 10
// CHECK-NEXT:    br i1 [[CMP140]], label %[[OMP_BODY_NEXT:.*]], label %[[OMP_BODY_CONTINUE:.*]]
// CHECK:       [[OMP_BODY_NEXT]]:
// CHECK-NEXT:    [[TMP56:%.*]] = load i32, ptr [[K]], align 4
// CHECK-NEXT:    [[CMP141:%.*]] = icmp ult i32 [[TMP56]], 10
// CHECK-NEXT:    br i1 [[CMP141]], label %[[OMP_BODY_NEXT142:.*]], label %[[OMP_BODY_CONTINUE]]
// CHECK:       [[OMP_BODY_NEXT142]]:
// CHECK-NEXT:    br label %[[OMP_BODY_CONTINUE]]
// CHECK:       [[OMP_BODY_CONTINUE]]:
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_INC:.*]]
// CHECK:       [[OMP_INNER_FOR_INC]]:
// CHECK-NEXT:    [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[ADD143:%.*]] = add nsw i64 [[TMP57]], 1
// CHECK-NEXT:    store i64 [[ADD143]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND]]
// CHECK:       [[OMP_INNER_FOR_END]]:
// CHECK-NEXT:    br label %[[OMP_LOOP_EXIT:.*]]
// CHECK:       [[OMP_LOOP_EXIT]]:
// CHECK-NEXT:    [[TMP58:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP59:%.*]] = load i32, ptr [[TMP58]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP59]])
// CHECK-NEXT:    ret void
void triangular_loop_1() {
#pragma omp parallel for collapse(3)
  for (unsigned int i = 0; i < 10; ++i)
    for (unsigned int j = i + 1; j < 10; ++j)
      for (unsigned int k = j + 1; k < 10; ++k)
	;
}

// CHECK-LABEL: define internal void @_Z17triangular_loop_2v.omp_outlined(
// CHECK-SAME: ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-NEXT:  [[ENTRY:.*:]]
// CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP1:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP2:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MIN:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MAX:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTMIN_LESS_MAX:%.*]] = alloca i8, align 1
// CHECK-NEXT:    [[DOTLOWER:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MIN4:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MAX7:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTMIN_LESS_MAX13:%.*]] = alloca i8, align 1
// CHECK-NEXT:    [[DOTLOWER16:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[K:%.*]] = alloca i32, align 4
// CHECK-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-NEXT:    store i32 0, ptr [[TMP]], align 4
// CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP0]], 1
// CHECK-NEXT:    store i32 [[ADD]], ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    store i32 9, ptr [[TMP]], align 4
// CHECK-NEXT:    [[TMP100:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD3:%.*]] = add i32 [[TMP100]], 1
// CHECK-NEXT:    store i32 [[ADD3]], ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]]
// CHECK-NEXT:    [[STOREDV:%.*]] = zext i1 [[CMP]] to i8
// CHECK-NEXT:    store i8 [[STOREDV]], ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK-NEXT:    br i1 [[LOADEDV]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]]
// CHECK:       [[COND_TRUE]]:
// CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    br label %[[COND_END:.*]]
// CHECK:       [[COND_FALSE]]:
// CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    br label %[[COND_END]]
// CHECK:       [[COND_END]]:
// CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP5]], %[[COND_TRUE]] ], [ [[TMP6]], %[[COND_FALSE]] ]
// CHECK-NEXT:    store i32 [[COND]], ptr [[TMP]], align 4
// CHECK-NEXT:    store i32 [[COND]], ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD5:%.*]] = add i32 [[TMP7]], 1
// CHECK-NEXT:    store i32 [[ADD5]], ptr [[TMP1]], align 4
// CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK-NEXT:    store i32 [[ADD6]], ptr [[DOTLB_MIN4]], align 4
// CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], 1
// CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    [[ADD9:%.*]] = add i32 [[TMP10]], 1
// CHECK-NEXT:    [[SUB:%.*]] = sub i32 10, [[ADD9]]
// CHECK-NEXT:    [[SUB10:%.*]] = sub i32 [[SUB]], 1
// CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[SUB10]], 2
// CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[DIV]], 2
// CHECK-NEXT:    [[ADD11:%.*]] = add i32 [[ADD8]], [[MUL]]
// CHECK-NEXT:    store i32 [[ADD11]], ptr [[TMP1]], align 4
// CHECK-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
// CHECK-NEXT:    store i32 [[ADD12]], ptr [[DOTLB_MAX7]], align 4
// CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTLB_MIN4]], align 4
// CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLB_MAX7]], align 4
// CHECK-NEXT:    [[CMP14:%.*]] = icmp ult i32 [[TMP12]], [[TMP13]]
// CHECK-NEXT:    [[STOREDV15:%.*]] = zext i1 [[CMP14]] to i8
// CHECK-NEXT:    store i8 [[STOREDV15]], ptr [[DOTMIN_LESS_MAX13]], align 1
// CHECK-NEXT:    [[TMP14:%.*]] = load i8, ptr [[DOTMIN_LESS_MAX13]], align 1
// CHECK-NEXT:    [[LOADEDV17:%.*]] = trunc i8 [[TMP14]] to i1
// CHECK-NEXT:    br i1 [[LOADEDV17]], label %[[COND_TRUE18:.*]], label %[[COND_FALSE19:.*]]
// CHECK:       [[COND_TRUE18]]:
// CHECK-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTLB_MIN4]], align 4
// CHECK-NEXT:    br label %[[COND_END20:.*]]
// CHECK:       [[COND_FALSE19]]:
// CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTLB_MAX7]], align 4
// CHECK-NEXT:    br label %[[COND_END20]]
// CHECK:       [[COND_END20]]:
// CHECK-NEXT:    [[COND21:%.*]] = phi i32 [ [[TMP15]], %[[COND_TRUE18]] ], [ [[TMP16]], %[[COND_FALSE19]] ]
// CHECK-NEXT:    store i32 [[COND21]], ptr [[TMP1]], align 4
// CHECK-NEXT:    store i32 [[COND21]], ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB22:%.*]] = sub i32 10, [[TMP17]]
// CHECK-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
// CHECK-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 2
// CHECK-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 2
// CHECK-NEXT:    [[CONV:%.*]] = zext i32 [[DIV25]] to i64
// CHECK-NEXT:    [[MUL26:%.*]] = mul nsw i64 10, [[CONV]]
// CHECK-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB27:%.*]] = sub i32 10, [[TMP18]]
// CHECK-NEXT:    [[ADD28:%.*]] = add i32 [[SUB27]], 1
// CHECK-NEXT:    [[CONV29:%.*]] = zext i32 [[ADD28]] to i64
// CHECK-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[MUL26]], [[CONV29]]
// CHECK-NEXT:    [[SUB31:%.*]] = sub nsw i64 [[MUL30]], 1
// CHECK-NEXT:    store i64 [[SUB31]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 [[TMP19]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP21]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    [[CMP32:%.*]] = icmp sgt i64 [[TMP22]], [[TMP23]]
// CHECK-NEXT:    br i1 [[CMP32]], label %[[COND_TRUE33:.*]], label %[[COND_FALSE34:.*]]
// CHECK:       [[COND_TRUE33]]:
// CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    br label %[[COND_END35:.*]]
// CHECK:       [[COND_FALSE34]]:
// CHECK-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    br label %[[COND_END35]]
// CHECK:       [[COND_END35]]:
// CHECK-NEXT:    [[COND36:%.*]] = phi i64 [ [[TMP24]], %[[COND_TRUE33]] ], [ [[TMP25]], %[[COND_FALSE34]] ]
// CHECK-NEXT:    store i64 [[COND36]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    store i64 [[TMP26]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND:.*]]
// CHECK:       [[OMP_INNER_FOR_COND]]:
// CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP28:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[CMP37:%.*]] = icmp sle i64 [[TMP27]], [[TMP28]]
// CHECK-NEXT:    br i1 [[CMP37]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]]
// CHECK:       [[OMP_INNER_FOR_BODY]]:
// CHECK-NEXT:    [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB38:%.*]] = sub i32 10, [[TMP30]]
// CHECK-NEXT:    [[SUB39:%.*]] = sub i32 [[SUB38]], 1
// CHECK-NEXT:    [[ADD40:%.*]] = add i32 [[SUB39]], 2
// CHECK-NEXT:    [[DIV41:%.*]] = udiv i32 [[ADD40]], 2
// CHECK-NEXT:    [[MUL42:%.*]] = mul i32 1, [[DIV41]]
// CHECK-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB43:%.*]] = sub i32 10, [[TMP31]]
// CHECK-NEXT:    [[ADD44:%.*]] = add i32 [[SUB43]], 1
// CHECK-NEXT:    [[MUL45:%.*]] = mul i32 [[MUL42]], [[ADD44]]
// CHECK-NEXT:    [[CONV46:%.*]] = zext i32 [[MUL45]] to i64
// CHECK-NEXT:    [[DIV47:%.*]] = sdiv i64 [[TMP29]], [[CONV46]]
// CHECK-NEXT:    [[MUL48:%.*]] = mul nsw i64 [[DIV47]], 1
// CHECK-NEXT:    [[ADD49:%.*]] = add nsw i64 0, [[MUL48]]
// CHECK-NEXT:    [[CONV50:%.*]] = trunc i64 [[ADD49]] to i32
// CHECK-NEXT:    store i32 [[CONV50]], ptr [[I]], align 4
// CHECK-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I]], align 4
// CHECK-NEXT:    [[ADD51:%.*]] = add i32 [[TMP32]], 1
// CHECK-NEXT:    [[CONV52:%.*]] = sext i32 [[ADD51]] to i64
// CHECK-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB53:%.*]] = sub i32 10, [[TMP35]]
// CHECK-NEXT:    [[SUB54:%.*]] = sub i32 [[SUB53]], 1
// CHECK-NEXT:    [[ADD55:%.*]] = add i32 [[SUB54]], 2
// CHECK-NEXT:    [[DIV56:%.*]] = udiv i32 [[ADD55]], 2
// CHECK-NEXT:    [[MUL57:%.*]] = mul i32 1, [[DIV56]]
// CHECK-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB58:%.*]] = sub i32 10, [[TMP36]]
// CHECK-NEXT:    [[ADD59:%.*]] = add i32 [[SUB58]], 1
// CHECK-NEXT:    [[MUL60:%.*]] = mul i32 [[MUL57]], [[ADD59]]
// CHECK-NEXT:    [[CONV61:%.*]] = zext i32 [[MUL60]] to i64
// CHECK-NEXT:    [[DIV62:%.*]] = sdiv i64 [[TMP34]], [[CONV61]]
// CHECK-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB63:%.*]] = sub i32 10, [[TMP37]]
// CHECK-NEXT:    [[SUB64:%.*]] = sub i32 [[SUB63]], 1
// CHECK-NEXT:    [[ADD65:%.*]] = add i32 [[SUB64]], 2
// CHECK-NEXT:    [[DIV66:%.*]] = udiv i32 [[ADD65]], 2
// CHECK-NEXT:    [[MUL67:%.*]] = mul i32 1, [[DIV66]]
// CHECK-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB68:%.*]] = sub i32 10, [[TMP38]]
// CHECK-NEXT:    [[ADD69:%.*]] = add i32 [[SUB68]], 1
// CHECK-NEXT:    [[MUL70:%.*]] = mul i32 [[MUL67]], [[ADD69]]
// CHECK-NEXT:    [[CONV71:%.*]] = zext i32 [[MUL70]] to i64
// CHECK-NEXT:    [[MUL72:%.*]] = mul nsw i64 [[DIV62]], [[CONV71]]
// CHECK-NEXT:    [[SUB73:%.*]] = sub nsw i64 [[TMP33]], [[MUL72]]
// CHECK-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB74:%.*]] = sub i32 10, [[TMP39]]
// CHECK-NEXT:    [[ADD75:%.*]] = add i32 [[SUB74]], 1
// CHECK-NEXT:    [[MUL76:%.*]] = mul i32 1, [[ADD75]]
// CHECK-NEXT:    [[CONV77:%.*]] = zext i32 [[MUL76]] to i64
// CHECK-NEXT:    [[DIV78:%.*]] = sdiv i64 [[SUB73]], [[CONV77]]
// CHECK-NEXT:    [[MUL79:%.*]] = mul nsw i64 [[DIV78]], 2
// CHECK-NEXT:    [[ADD80:%.*]] = add nsw i64 [[CONV52]], [[MUL79]]
// CHECK-NEXT:    [[CONV81:%.*]] = trunc i64 [[ADD80]] to i32
// CHECK-NEXT:    store i32 [[CONV81]], ptr [[J]], align 4
// CHECK-NEXT:    [[TMP40:%.*]] = load i32, ptr [[J]], align 4
// CHECK-NEXT:    [[ADD82:%.*]] = add nsw i32 [[TMP40]], 1
// CHECK-NEXT:    [[CONV83:%.*]] = zext i32 [[ADD82]] to i64
// CHECK-NEXT:    [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB84:%.*]] = sub i32 10, [[TMP43]]
// CHECK-NEXT:    [[SUB85:%.*]] = sub i32 [[SUB84]], 1
// CHECK-NEXT:    [[ADD86:%.*]] = add i32 [[SUB85]], 2
// CHECK-NEXT:    [[DIV87:%.*]] = udiv i32 [[ADD86]], 2
// CHECK-NEXT:    [[MUL88:%.*]] = mul i32 1, [[DIV87]]
// CHECK-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB89:%.*]] = sub i32 10, [[TMP44]]
// CHECK-NEXT:    [[ADD90:%.*]] = add i32 [[SUB89]], 1
// CHECK-NEXT:    [[MUL91:%.*]] = mul i32 [[MUL88]], [[ADD90]]
// CHECK-NEXT:    [[CONV92:%.*]] = zext i32 [[MUL91]] to i64
// CHECK-NEXT:    [[DIV93:%.*]] = sdiv i64 [[TMP42]], [[CONV92]]
// CHECK-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB94:%.*]] = sub i32 10, [[TMP45]]
// CHECK-NEXT:    [[SUB95:%.*]] = sub i32 [[SUB94]], 1
// CHECK-NEXT:    [[ADD96:%.*]] = add i32 [[SUB95]], 2
// CHECK-NEXT:    [[DIV97:%.*]] = udiv i32 [[ADD96]], 2
// CHECK-NEXT:    [[MUL98:%.*]] = mul i32 1, [[DIV97]]
// CHECK-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB99:%.*]] = sub i32 10, [[TMP46]]
// CHECK-NEXT:    [[ADD100:%.*]] = add i32 [[SUB99]], 1
// CHECK-NEXT:    [[MUL101:%.*]] = mul i32 [[MUL98]], [[ADD100]]
// CHECK-NEXT:    [[CONV102:%.*]] = zext i32 [[MUL101]] to i64
// CHECK-NEXT:    [[MUL103:%.*]] = mul nsw i64 [[DIV93]], [[CONV102]]
// CHECK-NEXT:    [[SUB104:%.*]] = sub nsw i64 [[TMP41]], [[MUL103]]
// CHECK-NEXT:    [[TMP47:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP49:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB105:%.*]] = sub i32 10, [[TMP49]]
// CHECK-NEXT:    [[SUB106:%.*]] = sub i32 [[SUB105]], 1
// CHECK-NEXT:    [[ADD107:%.*]] = add i32 [[SUB106]], 2
// CHECK-NEXT:    [[DIV108:%.*]] = udiv i32 [[ADD107]], 2
// CHECK-NEXT:    [[MUL109:%.*]] = mul i32 1, [[DIV108]]
// CHECK-NEXT:    [[TMP50:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB110:%.*]] = sub i32 10, [[TMP50]]
// CHECK-NEXT:    [[ADD111:%.*]] = add i32 [[SUB110]], 1
// CHECK-NEXT:    [[MUL112:%.*]] = mul i32 [[MUL109]], [[ADD111]]
// CHECK-NEXT:    [[CONV113:%.*]] = zext i32 [[MUL112]] to i64
// CHECK-NEXT:    [[DIV114:%.*]] = sdiv i64 [[TMP48]], [[CONV113]]
// CHECK-NEXT:    [[TMP51:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB115:%.*]] = sub i32 10, [[TMP51]]
// CHECK-NEXT:    [[SUB116:%.*]] = sub i32 [[SUB115]], 1
// CHECK-NEXT:    [[ADD117:%.*]] = add i32 [[SUB116]], 2
// CHECK-NEXT:    [[DIV118:%.*]] = udiv i32 [[ADD117]], 2
// CHECK-NEXT:    [[MUL119:%.*]] = mul i32 1, [[DIV118]]
// CHECK-NEXT:    [[TMP52:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB120:%.*]] = sub i32 10, [[TMP52]]
// CHECK-NEXT:    [[ADD121:%.*]] = add i32 [[SUB120]], 1
// CHECK-NEXT:    [[MUL122:%.*]] = mul i32 [[MUL119]], [[ADD121]]
// CHECK-NEXT:    [[CONV123:%.*]] = zext i32 [[MUL122]] to i64
// CHECK-NEXT:    [[MUL124:%.*]] = mul nsw i64 [[DIV114]], [[CONV123]]
// CHECK-NEXT:    [[SUB125:%.*]] = sub nsw i64 [[TMP47]], [[MUL124]]
// CHECK-NEXT:    [[TMP53:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB126:%.*]] = sub i32 10, [[TMP53]]
// CHECK-NEXT:    [[ADD127:%.*]] = add i32 [[SUB126]], 1
// CHECK-NEXT:    [[MUL128:%.*]] = mul i32 1, [[ADD127]]
// CHECK-NEXT:    [[CONV129:%.*]] = zext i32 [[MUL128]] to i64
// CHECK-NEXT:    [[DIV130:%.*]] = sdiv i64 [[SUB125]], [[CONV129]]
// CHECK-NEXT:    [[TMP54:%.*]] = load i32, ptr [[DOTLOWER16]], align 4
// CHECK-NEXT:    [[SUB131:%.*]] = sub i32 10, [[TMP54]]
// CHECK-NEXT:    [[ADD132:%.*]] = add i32 [[SUB131]], 1
// CHECK-NEXT:    [[MUL133:%.*]] = mul i32 1, [[ADD132]]
// CHECK-NEXT:    [[CONV134:%.*]] = zext i32 [[MUL133]] to i64
// CHECK-NEXT:    [[MUL135:%.*]] = mul nsw i64 [[DIV130]], [[CONV134]]
// CHECK-NEXT:    [[SUB136:%.*]] = sub nsw i64 [[SUB104]], [[MUL135]]
// CHECK-NEXT:    [[MUL137:%.*]] = mul nsw i64 [[SUB136]], 1
// CHECK-NEXT:    [[ADD138:%.*]] = add nsw i64 [[CONV83]], [[MUL137]]
// CHECK-NEXT:    [[CONV139:%.*]] = trunc i64 [[ADD138]] to i32
// CHECK-NEXT:    store i32 [[CONV139]], ptr [[K]], align 4
// CHECK-NEXT:    [[TMP55:%.*]] = load i32, ptr [[J]], align 4
// CHECK-NEXT:    [[CMP140:%.*]] = icmp slt i32 [[TMP55]], 10
// CHECK-NEXT:    br i1 [[CMP140]], label %[[OMP_BODY_NEXT:.*]], label %[[OMP_BODY_CONTINUE:.*]]
// CHECK:       [[OMP_BODY_NEXT]]:
// CHECK-NEXT:    [[TMP56:%.*]] = load i32, ptr [[K]], align 4
// CHECK-NEXT:    [[CMP141:%.*]] = icmp ult i32 [[TMP56]], 10
// CHECK-NEXT:    br i1 [[CMP141]], label %[[OMP_BODY_NEXT142:.*]], label %[[OMP_BODY_CONTINUE]]
// CHECK:       [[OMP_BODY_NEXT142]]:
// CHECK-NEXT:    br label %[[OMP_BODY_CONTINUE]]
// CHECK:       [[OMP_BODY_CONTINUE]]:
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_INC:.*]]
// CHECK:       [[OMP_INNER_FOR_INC]]:
// CHECK-NEXT:    [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[ADD143:%.*]] = add nsw i64 [[TMP57]], 1
// CHECK-NEXT:    store i64 [[ADD143]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND]]
// CHECK:       [[OMP_INNER_FOR_END]]:
// CHECK-NEXT:    br label %[[OMP_LOOP_EXIT:.*]]
// CHECK:       [[OMP_LOOP_EXIT]]:
// CHECK-NEXT:    [[TMP58:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP59:%.*]] = load i32, ptr [[TMP58]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP59]])
// CHECK-NEXT:    ret void
void triangular_loop_2() {
#pragma omp parallel for collapse(3)
  for (unsigned int i = 0; i < 10; ++i)
    for (int j = i + 1; j < 10; j += 2)
      for (unsigned int k = j + 1; k < 10; ++k)
	;
}

// CHECK-LABEL: define internal void @{{.*}}triangular_loop_3v_l810.omp_outlined(
// CHECK-SAME: ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-NEXT:  [[ENTRY:.*:]]
// CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MIN:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MAX:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTMIN_LESS_MAX:%.*]] = alloca i8, align 1
// CHECK-NEXT:    [[DOTLOWER:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[K:%.*]] = alloca i32, align 4
// CHECK-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-NEXT:    store i32 0, ptr [[TMP]], align 4
// CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    store i32 [[TMP0]], ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    store i32 9, ptr [[TMP]], align 4
// CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP]], align 4
// CHECK-NEXT:    store i32 [[TMP1]], ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[TMP2]], [[TMP3]]
// CHECK-NEXT:    [[STOREDV:%.*]] = zext i1 [[CMP]] to i8
// CHECK-NEXT:    store i8 [[STOREDV]], ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK-NEXT:    br i1 [[LOADEDV]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]]
// CHECK:       [[COND_TRUE]]:
// CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    br label %[[COND_END:.*]]
// CHECK:       [[COND_FALSE]]:
// CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    br label %[[COND_END]]
// CHECK:       [[COND_END]]:
// CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP5]], %[[COND_TRUE]] ], [ [[TMP6]], %[[COND_FALSE]] ]
// CHECK-NEXT:    store i32 [[COND]], ptr [[TMP]], align 4
// CHECK-NEXT:    store i32 [[COND]], ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB:%.*]] = sub i32 10, [[TMP7]]
// CHECK-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
// CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
// CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
// CHECK-NEXT:    [[CONV:%.*]] = zext i32 [[DIV]] to i64
// CHECK-NEXT:    [[MUL:%.*]] = mul nsw i64 100, [[CONV]]
// CHECK-NEXT:    [[SUB4:%.*]] = sub nsw i64 [[MUL]], 1
// CHECK-NEXT:    store i64 [[SUB4]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    [[CMP5:%.*]] = icmp sgt i64 [[TMP11]], [[TMP12]]
// CHECK-NEXT:    br i1 [[CMP5]], label %[[COND_TRUE6:.*]], label %[[COND_FALSE7:.*]]
// CHECK:       [[COND_TRUE6]]:
// CHECK-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    br label %[[COND_END8:.*]]
// CHECK:       [[COND_FALSE7]]:
// CHECK-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    br label %[[COND_END8]]
// CHECK:       [[COND_END8]]:
// CHECK-NEXT:    [[COND9:%.*]] = phi i64 [ [[TMP13]], %[[COND_TRUE6]] ], [ [[TMP14]], %[[COND_FALSE7]] ]
// CHECK-NEXT:    store i64 [[COND9]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    store i64 [[TMP15]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND:.*]]
// CHECK:       [[OMP_INNER_FOR_COND]]:
// CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP16]], [[TMP17]]
// CHECK-NEXT:    br i1 [[CMP10]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]]
// CHECK:       [[OMP_INNER_FOR_BODY]]:
// CHECK-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB11:%.*]] = sub i32 10, [[TMP19]]
// CHECK-NEXT:    [[SUB12:%.*]] = sub i32 [[SUB11]], 1
// CHECK-NEXT:    [[ADD13:%.*]] = add i32 [[SUB12]], 1
// CHECK-NEXT:    [[DIV14:%.*]] = udiv i32 [[ADD13]], 1
// CHECK-NEXT:    [[MUL15:%.*]] = mul i32 10, [[DIV14]]
// CHECK-NEXT:    [[CONV16:%.*]] = zext i32 [[MUL15]] to i64
// CHECK-NEXT:    [[DIV17:%.*]] = sdiv i64 [[TMP18]], [[CONV16]]
// CHECK-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 1
// CHECK-NEXT:    [[ADD19:%.*]] = add nsw i64 0, [[MUL18]]
// CHECK-NEXT:    [[CONV20:%.*]] = trunc i64 [[ADD19]] to i32
// CHECK-NEXT:    store i32 [[CONV20]], ptr [[I]], align 4
// CHECK-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB21:%.*]] = sub i32 10, [[TMP22]]
// CHECK-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
// CHECK-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
// CHECK-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
// CHECK-NEXT:    [[MUL25:%.*]] = mul i32 10, [[DIV24]]
// CHECK-NEXT:    [[CONV26:%.*]] = zext i32 [[MUL25]] to i64
// CHECK-NEXT:    [[DIV27:%.*]] = sdiv i64 [[TMP21]], [[CONV26]]
// CHECK-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB28:%.*]] = sub i32 10, [[TMP23]]
// CHECK-NEXT:    [[SUB29:%.*]] = sub i32 [[SUB28]], 1
// CHECK-NEXT:    [[ADD30:%.*]] = add i32 [[SUB29]], 1
// CHECK-NEXT:    [[DIV31:%.*]] = udiv i32 [[ADD30]], 1
// CHECK-NEXT:    [[MUL32:%.*]] = mul i32 10, [[DIV31]]
// CHECK-NEXT:    [[CONV33:%.*]] = zext i32 [[MUL32]] to i64
// CHECK-NEXT:    [[MUL34:%.*]] = mul nsw i64 [[DIV27]], [[CONV33]]
// CHECK-NEXT:    [[SUB35:%.*]] = sub nsw i64 [[TMP20]], [[MUL34]]
// CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB36:%.*]] = sub i32 10, [[TMP24]]
// CHECK-NEXT:    [[SUB37:%.*]] = sub i32 [[SUB36]], 1
// CHECK-NEXT:    [[ADD38:%.*]] = add i32 [[SUB37]], 1
// CHECK-NEXT:    [[DIV39:%.*]] = udiv i32 [[ADD38]], 1
// CHECK-NEXT:    [[MUL40:%.*]] = mul i32 1, [[DIV39]]
// CHECK-NEXT:    [[CONV41:%.*]] = zext i32 [[MUL40]] to i64
// CHECK-NEXT:    [[DIV42:%.*]] = sdiv i64 [[SUB35]], [[CONV41]]
// CHECK-NEXT:    [[MUL43:%.*]] = mul nsw i64 [[DIV42]], 1
// CHECK-NEXT:    [[ADD44:%.*]] = add nsw i64 0, [[MUL43]]
// CHECK-NEXT:    [[CONV45:%.*]] = trunc i64 [[ADD44]] to i32
// CHECK-NEXT:    store i32 [[CONV45]], ptr [[J]], align 4
// CHECK-NEXT:    [[TMP25:%.*]] = load i32, ptr [[I]], align 4
// CHECK-NEXT:    [[CONV46:%.*]] = zext i32 [[TMP25]] to i64
// CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB47:%.*]] = sub i32 10, [[TMP28]]
// CHECK-NEXT:    [[SUB48:%.*]] = sub i32 [[SUB47]], 1
// CHECK-NEXT:    [[ADD49:%.*]] = add i32 [[SUB48]], 1
// CHECK-NEXT:    [[DIV50:%.*]] = udiv i32 [[ADD49]], 1
// CHECK-NEXT:    [[MUL51:%.*]] = mul i32 10, [[DIV50]]
// CHECK-NEXT:    [[CONV52:%.*]] = zext i32 [[MUL51]] to i64
// CHECK-NEXT:    [[DIV53:%.*]] = sdiv i64 [[TMP27]], [[CONV52]]
// CHECK-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB54:%.*]] = sub i32 10, [[TMP29]]
// CHECK-NEXT:    [[SUB55:%.*]] = sub i32 [[SUB54]], 1
// CHECK-NEXT:    [[ADD56:%.*]] = add i32 [[SUB55]], 1
// CHECK-NEXT:    [[DIV57:%.*]] = udiv i32 [[ADD56]], 1
// CHECK-NEXT:    [[MUL58:%.*]] = mul i32 10, [[DIV57]]
// CHECK-NEXT:    [[CONV59:%.*]] = zext i32 [[MUL58]] to i64
// CHECK-NEXT:    [[MUL60:%.*]] = mul nsw i64 [[DIV53]], [[CONV59]]
// CHECK-NEXT:    [[SUB61:%.*]] = sub nsw i64 [[TMP26]], [[MUL60]]
// CHECK-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB62:%.*]] = sub i32 10, [[TMP32]]
// CHECK-NEXT:    [[SUB63:%.*]] = sub i32 [[SUB62]], 1
// CHECK-NEXT:    [[ADD64:%.*]] = add i32 [[SUB63]], 1
// CHECK-NEXT:    [[DIV65:%.*]] = udiv i32 [[ADD64]], 1
// CHECK-NEXT:    [[MUL66:%.*]] = mul i32 10, [[DIV65]]
// CHECK-NEXT:    [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
// CHECK-NEXT:    [[DIV68:%.*]] = sdiv i64 [[TMP31]], [[CONV67]]
// CHECK-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB69:%.*]] = sub i32 10, [[TMP33]]
// CHECK-NEXT:    [[SUB70:%.*]] = sub i32 [[SUB69]], 1
// CHECK-NEXT:    [[ADD71:%.*]] = add i32 [[SUB70]], 1
// CHECK-NEXT:    [[DIV72:%.*]] = udiv i32 [[ADD71]], 1
// CHECK-NEXT:    [[MUL73:%.*]] = mul i32 10, [[DIV72]]
// CHECK-NEXT:    [[CONV74:%.*]] = zext i32 [[MUL73]] to i64
// CHECK-NEXT:    [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]
// CHECK-NEXT:    [[SUB76:%.*]] = sub nsw i64 [[TMP30]], [[MUL75]]
// CHECK-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB77:%.*]] = sub i32 10, [[TMP34]]
// CHECK-NEXT:    [[SUB78:%.*]] = sub i32 [[SUB77]], 1
// CHECK-NEXT:    [[ADD79:%.*]] = add i32 [[SUB78]], 1
// CHECK-NEXT:    [[DIV80:%.*]] = udiv i32 [[ADD79]], 1
// CHECK-NEXT:    [[MUL81:%.*]] = mul i32 1, [[DIV80]]
// CHECK-NEXT:    [[CONV82:%.*]] = zext i32 [[MUL81]] to i64
// CHECK-NEXT:    [[DIV83:%.*]] = sdiv i64 [[SUB76]], [[CONV82]]
// CHECK-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB84:%.*]] = sub i32 10, [[TMP35]]
// CHECK-NEXT:    [[SUB85:%.*]] = sub i32 [[SUB84]], 1
// CHECK-NEXT:    [[ADD86:%.*]] = add i32 [[SUB85]], 1
// CHECK-NEXT:    [[DIV87:%.*]] = udiv i32 [[ADD86]], 1
// CHECK-NEXT:    [[MUL88:%.*]] = mul i32 1, [[DIV87]]
// CHECK-NEXT:    [[CONV89:%.*]] = zext i32 [[MUL88]] to i64
// CHECK-NEXT:    [[MUL90:%.*]] = mul nsw i64 [[DIV83]], [[CONV89]]
// CHECK-NEXT:    [[SUB91:%.*]] = sub nsw i64 [[SUB61]], [[MUL90]]
// CHECK-NEXT:    [[MUL92:%.*]] = mul nsw i64 [[SUB91]], 1
// CHECK-NEXT:    [[ADD93:%.*]] = add nsw i64 [[CONV46]], [[MUL92]]
// CHECK-NEXT:    [[CONV94:%.*]] = trunc i64 [[ADD93]] to i32
// CHECK-NEXT:    store i32 [[CONV94]], ptr [[K]], align 4
// CHECK-NEXT:    [[TMP36:%.*]] = load i32, ptr [[K]], align 4
// CHECK-NEXT:    [[CMP95:%.*]] = icmp ult i32 [[TMP36]], 10
// CHECK-NEXT:    br i1 [[CMP95]], label %[[OMP_BODY_NEXT:.*]], label %[[OMP_BODY_CONTINUE:.*]]
// CHECK:       [[OMP_BODY_NEXT]]:
// CHECK-NEXT:    br label %[[OMP_BODY_CONTINUE]]
// CHECK:       [[OMP_BODY_CONTINUE]]:
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_INC:.*]]
// CHECK:       [[OMP_INNER_FOR_INC]]:
// CHECK-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[ADD96:%.*]] = add nsw i64 [[TMP37]], 1
// CHECK-NEXT:    store i64 [[ADD96]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND]]
// CHECK:       [[OMP_INNER_FOR_END]]:
// CHECK-NEXT:    br label %[[OMP_LOOP_EXIT:.*]]
// CHECK:       [[OMP_LOOP_EXIT]]:
// CHECK-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP39]])
// CHECK-NEXT:    ret void
void triangular_loop_3() {
#pragma omp target parallel loop collapse(3)
  for (unsigned int i = 0; i < 10; i++)
    for (int j = 0; j < 10; j++)
      for (unsigned k = i; k < 10; k++)
	;
}

// CHECK-LABEL: define internal void @_Z10mixed_loopv.omp_outlined(
// CHECK-SAME: ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-NEXT:  [[ENTRY:.*:]]
// CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP1:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP2:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MIN:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTLB_MAX:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTMIN_LESS_MAX:%.*]] = alloca i8, align 1
// CHECK-NEXT:    [[DOTLOWER:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
// CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[K:%.*]] = alloca i32, align 4
// CHECK-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-NEXT:    store i32 0, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK-NEXT:    store i32 [[ADD]], ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    store i32 9, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[TMP100:%.*]] = load i32, ptr [[TMP1]], align 4
// CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP100]], 1
// CHECK-NEXT:    store i32 [[ADD3]], ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP2]], [[TMP3]]
// CHECK-NEXT:    [[STOREDV:%.*]] = zext i1 [[CMP]] to i8
// CHECK-NEXT:    store i8 [[STOREDV]], ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTMIN_LESS_MAX]], align 1
// CHECK-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP4]] to i1
// CHECK-NEXT:    br i1 [[LOADEDV]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]]
// CHECK:       [[COND_TRUE]]:
// CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTLB_MIN]], align 4
// CHECK-NEXT:    br label %[[COND_END:.*]]
// CHECK:       [[COND_FALSE]]:
// CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTLB_MAX]], align 4
// CHECK-NEXT:    br label %[[COND_END]]
// CHECK:       [[COND_END]]:
// CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP5]], %[[COND_TRUE]] ], [ [[TMP6]], %[[COND_FALSE]] ]
// CHECK-NEXT:    store i32 [[COND]], ptr [[TMP1]], align 4
// CHECK-NEXT:    store i32 [[COND]], ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB:%.*]] = sub i32 10, [[TMP7]]
// CHECK-NEXT:    [[ADD4:%.*]] = add i32 [[SUB]], 1
// CHECK-NEXT:    [[CONV:%.*]] = zext i32 [[ADD4]] to i64
// CHECK-NEXT:    [[MUL:%.*]] = mul nsw i64 100, [[CONV]]
// CHECK-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
// CHECK-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
// CHECK-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    [[CMP6:%.*]] = icmp sgt i64 [[TMP11]], [[TMP12]]
// CHECK-NEXT:    br i1 [[CMP6]], label %[[COND_TRUE7:.*]], label %[[COND_FALSE8:.*]]
// CHECK:       [[COND_TRUE7]]:
// CHECK-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_]], align 8
// CHECK-NEXT:    br label %[[COND_END9:.*]]
// CHECK:       [[COND_FALSE8]]:
// CHECK-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    br label %[[COND_END9]]
// CHECK:       [[COND_END9]]:
// CHECK-NEXT:    [[COND10:%.*]] = phi i64 [ [[TMP13]], %[[COND_TRUE7]] ], [ [[TMP14]], %[[COND_FALSE8]] ]
// CHECK-NEXT:    store i64 [[COND10]], ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK-NEXT:    store i64 [[TMP15]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND:.*]]
// CHECK:       [[OMP_INNER_FOR_COND]]:
// CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
// CHECK-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP16]], [[TMP17]]
// CHECK-NEXT:    br i1 [[CMP11]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]]
// CHECK:       [[OMP_INNER_FOR_BODY]]:
// CHECK-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB12:%.*]] = sub i32 10, [[TMP19]]
// CHECK-NEXT:    [[ADD13:%.*]] = add i32 [[SUB12]], 1
// CHECK-NEXT:    [[MUL14:%.*]] = mul i32 10, [[ADD13]]
// CHECK-NEXT:    [[CONV15:%.*]] = zext i32 [[MUL14]] to i64
// CHECK-NEXT:    [[DIV:%.*]] = sdiv i64 [[TMP18]], [[CONV15]]
// CHECK-NEXT:    [[MUL16:%.*]] = mul nsw i64 [[DIV]], 1
// CHECK-NEXT:    [[ADD17:%.*]] = add nsw i64 0, [[MUL16]]
// CHECK-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD17]] to i32
// CHECK-NEXT:    store i32 [[CONV18]], ptr [[I]], align 4
// CHECK-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB19:%.*]] = sub i32 10, [[TMP22]]
// CHECK-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
// CHECK-NEXT:    [[MUL21:%.*]] = mul i32 10, [[ADD20]]
// CHECK-NEXT:    [[CONV22:%.*]] = zext i32 [[MUL21]] to i64
// CHECK-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP21]], [[CONV22]]
// CHECK-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB24:%.*]] = sub i32 10, [[TMP23]]
// CHECK-NEXT:    [[ADD25:%.*]] = add i32 [[SUB24]], 1
// CHECK-NEXT:    [[MUL26:%.*]] = mul i32 10, [[ADD25]]
// CHECK-NEXT:    [[CONV27:%.*]] = zext i32 [[MUL26]] to i64
// CHECK-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
// CHECK-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP20]], [[MUL28]]
// CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB30:%.*]] = sub i32 10, [[TMP24]]
// CHECK-NEXT:    [[ADD31:%.*]] = add i32 [[SUB30]], 1
// CHECK-NEXT:    [[MUL32:%.*]] = mul i32 1, [[ADD31]]
// CHECK-NEXT:    [[CONV33:%.*]] = zext i32 [[MUL32]] to i64
// CHECK-NEXT:    [[DIV34:%.*]] = sdiv i64 [[SUB29]], [[CONV33]]
// CHECK-NEXT:    [[MUL35:%.*]] = mul nsw i64 [[DIV34]], 1
// CHECK-NEXT:    [[ADD36:%.*]] = add nsw i64 0, [[MUL35]]
// CHECK-NEXT:    [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32
// CHECK-NEXT:    store i32 [[CONV37]], ptr [[J]], align 4
// CHECK-NEXT:    [[TMP25:%.*]] = load i32, ptr [[J]], align 4
// CHECK-NEXT:    [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1
// CHECK-NEXT:    [[CONV39:%.*]] = sext i32 [[ADD38]] to i64
// CHECK-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB40:%.*]] = sub i32 10, [[TMP28]]
// CHECK-NEXT:    [[ADD41:%.*]] = add i32 [[SUB40]], 1
// CHECK-NEXT:    [[MUL42:%.*]] = mul i32 10, [[ADD41]]
// CHECK-NEXT:    [[CONV43:%.*]] = zext i32 [[MUL42]] to i64
// CHECK-NEXT:    [[DIV44:%.*]] = sdiv i64 [[TMP27]], [[CONV43]]
// CHECK-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB45:%.*]] = sub i32 10, [[TMP29]]
// CHECK-NEXT:    [[ADD46:%.*]] = add i32 [[SUB45]], 1
// CHECK-NEXT:    [[MUL47:%.*]] = mul i32 10, [[ADD46]]
// CHECK-NEXT:    [[CONV48:%.*]] = zext i32 [[MUL47]] to i64
// CHECK-NEXT:    [[MUL49:%.*]] = mul nsw i64 [[DIV44]], [[CONV48]]
// CHECK-NEXT:    [[SUB50:%.*]] = sub nsw i64 [[TMP26]], [[MUL49]]
// CHECK-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB51:%.*]] = sub i32 10, [[TMP32]]
// CHECK-NEXT:    [[ADD52:%.*]] = add i32 [[SUB51]], 1
// CHECK-NEXT:    [[MUL53:%.*]] = mul i32 10, [[ADD52]]
// CHECK-NEXT:    [[CONV54:%.*]] = zext i32 [[MUL53]] to i64
// CHECK-NEXT:    [[DIV55:%.*]] = sdiv i64 [[TMP31]], [[CONV54]]
// CHECK-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB56:%.*]] = sub i32 10, [[TMP33]]
// CHECK-NEXT:    [[ADD57:%.*]] = add i32 [[SUB56]], 1
// CHECK-NEXT:    [[MUL58:%.*]] = mul i32 10, [[ADD57]]
// CHECK-NEXT:    [[CONV59:%.*]] = zext i32 [[MUL58]] to i64
// CHECK-NEXT:    [[MUL60:%.*]] = mul nsw i64 [[DIV55]], [[CONV59]]
// CHECK-NEXT:    [[SUB61:%.*]] = sub nsw i64 [[TMP30]], [[MUL60]]
// CHECK-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB62:%.*]] = sub i32 10, [[TMP34]]
// CHECK-NEXT:    [[ADD63:%.*]] = add i32 [[SUB62]], 1
// CHECK-NEXT:    [[MUL64:%.*]] = mul i32 1, [[ADD63]]
// CHECK-NEXT:    [[CONV65:%.*]] = zext i32 [[MUL64]] to i64
// CHECK-NEXT:    [[DIV66:%.*]] = sdiv i64 [[SUB61]], [[CONV65]]
// CHECK-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTLOWER]], align 4
// CHECK-NEXT:    [[SUB67:%.*]] = sub i32 10, [[TMP35]]
// CHECK-NEXT:    [[ADD68:%.*]] = add i32 [[SUB67]], 1
// CHECK-NEXT:    [[MUL69:%.*]] = mul i32 1, [[ADD68]]
// CHECK-NEXT:    [[CONV70:%.*]] = zext i32 [[MUL69]] to i64
// CHECK-NEXT:    [[MUL71:%.*]] = mul nsw i64 [[DIV66]], [[CONV70]]
// CHECK-NEXT:    [[SUB72:%.*]] = sub nsw i64 [[SUB50]], [[MUL71]]
// CHECK-NEXT:    [[MUL73:%.*]] = mul nsw i64 [[SUB72]], 1
// CHECK-NEXT:    [[ADD74:%.*]] = add nsw i64 [[CONV39]], [[MUL73]]
// CHECK-NEXT:    [[CONV75:%.*]] = trunc i64 [[ADD74]] to i32
// CHECK-NEXT:    store i32 [[CONV75]], ptr [[K]], align 4
// CHECK-NEXT:    [[TMP36:%.*]] = load i32, ptr [[K]], align 4
// CHECK-NEXT:    [[CMP76:%.*]] = icmp slt i32 [[TMP36]], 10
// CHECK-NEXT:    br i1 [[CMP76]], label %[[OMP_BODY_NEXT:.*]], label %[[OMP_BODY_CONTINUE:.*]]
// CHECK:       [[OMP_BODY_NEXT]]:
// CHECK-NEXT:    br label %[[OMP_BODY_CONTINUE]]
// CHECK:       [[OMP_BODY_CONTINUE]]:
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_INC:.*]]
// CHECK:       [[OMP_INNER_FOR_INC]]:
// CHECK-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    [[ADD77:%.*]] = add nsw i64 [[TMP37]], 1
// CHECK-NEXT:    store i64 [[ADD77]], ptr [[DOTOMP_IV]], align 8
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND]]
// CHECK:       [[OMP_INNER_FOR_END]]:
// CHECK-NEXT:    br label %[[OMP_LOOP_EXIT:.*]]
// CHECK:       [[OMP_LOOP_EXIT]]:
// CHECK-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP39]])
// CHECK-NEXT:    ret void
void mixed_loop() {
#pragma omp parallel for collapse(3)
  for (int i = 0; i < 10; ++i)
    for (int j = 0; j < 10; ++j)
      for (int k = j + 1; k < 10; ++k)
	;
}

// CHECK-LABEL: define internal void @_Z16rectangular_loopv.omp_outlined(
// CHECK-SAME: ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-NEXT:  [[ENTRY:.*:]]
// CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP1:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[TMP2:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
// CHECK-NEXT:    [[K:%.*]] = alloca i32, align 4
// CHECK-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-NEXT:    store i32 999, ptr [[DOTOMP_UB]], align 4
// CHECK-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 999
// CHECK-NEXT:    br i1 [[CMP]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]]
// CHECK:       [[COND_TRUE]]:
// CHECK-NEXT:    br label %[[COND_END:.*]]
// CHECK:       [[COND_FALSE]]:
// CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-NEXT:    br label %[[COND_END]]
// CHECK:       [[COND_END]]:
// CHECK-NEXT:    [[COND:%.*]] = phi i32 [ 999, %[[COND_TRUE]] ], [ [[TMP3]], %[[COND_FALSE]] ]
// CHECK-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
// CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND:.*]]
// CHECK:       [[OMP_INNER_FOR_COND]]:
// CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-NEXT:    br i1 [[CMP3]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]]
// CHECK:       [[OMP_INNER_FOR_BODY]]:
// CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP7]], 100
// CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
// CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP9]], 100
// CHECK-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 100
// CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP8]], [[MUL5]]
// CHECK-NEXT:    [[DIV6:%.*]] = sdiv i32 [[SUB]], 10
// CHECK-NEXT:    [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 1
// CHECK-NEXT:    [[ADD8:%.*]] = add nsw i32 0, [[MUL7]]
// CHECK-NEXT:    store i32 [[ADD8]], ptr [[J]], align 4
// CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[DIV9:%.*]] = sdiv i32 [[TMP11]], 100
// CHECK-NEXT:    [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 100
// CHECK-NEXT:    [[SUB11:%.*]] = sub nsw i32 [[TMP10]], [[MUL10]]
// CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[DIV12:%.*]] = sdiv i32 [[TMP13]], 100
// CHECK-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 100
// CHECK-NEXT:    [[SUB14:%.*]] = sub nsw i32 [[TMP12]], [[MUL13]]
// CHECK-NEXT:    [[DIV15:%.*]] = sdiv i32 [[SUB14]], 10
// CHECK-NEXT:    [[MUL16:%.*]] = mul nsw i32 [[DIV15]], 10
// CHECK-NEXT:    [[SUB17:%.*]] = sub nsw i32 [[SUB11]], [[MUL16]]
// CHECK-NEXT:    [[MUL18:%.*]] = mul nsw i32 [[SUB17]], 1
// CHECK-NEXT:    [[ADD19:%.*]] = add nsw i32 0, [[MUL18]]
// CHECK-NEXT:    store i32 [[ADD19]], ptr [[K]], align 4
// CHECK-NEXT:    br label %[[OMP_BODY_CONTINUE:.*]]
// CHECK:       [[OMP_BODY_CONTINUE]]:
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_INC:.*]]
// CHECK:       [[OMP_INNER_FOR_INC]]:
// CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    [[ADD20:%.*]] = add nsw i32 [[TMP14]], 1
// CHECK-NEXT:    store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4
// CHECK-NEXT:    br label %[[OMP_INNER_FOR_COND]]
// CHECK:       [[OMP_INNER_FOR_END]]:
// CHECK-NEXT:    br label %[[OMP_LOOP_EXIT:.*]]
// CHECK:       [[OMP_LOOP_EXIT]]:
// CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
// CHECK-NEXT:    ret void
void rectangular_loop() {
#pragma omp parallel for collapse(3)
  for (int i = 0; i < 10; ++i)
    for (int j = 0; j < 10; ++j)
      for (int k = 0; k < 10; ++k)
        ;
}