9f7f3d6548
This PR adds support for loading and storing volatile bit-field members according to the AAPCS specification. > A volatile bit-field must always be accessed using an access width appropriate to the type of its container, except when any of the following are true: > > * The bit-field container overlaps with a zero-length bit-field. > * The bit-field container overlaps with a non-bit-field member. For example, if a bit-field is declared as `int`, the load/store must use a 32-bit access, even if the field itself is only 3 bits wide.
286 lines
14 KiB
C
286 lines
14 KiB
C
// RUN: %clang_cc1 -triple aarch64-unknown-linux-gnu -fclangir -emit-cir -fdump-record-layouts %s -o %t.cir 1> %t.cirlayout
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// RUN: FileCheck --input-file=%t.cirlayout %s --check-prefix=CIR-LAYOUT
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// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR
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// RUN: %clang_cc1 -triple aarch64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
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// RUN: %clang_cc1 -triple aarch64-unknown-linux-gnu -emit-llvm -fdump-record-layouts %s -o %t.ll 1> %t.ogcglayout
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// RUN: FileCheck --input-file=%t.ogcglayout %s --check-prefix=OGCG-LAYOUT
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// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG
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typedef struct {
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unsigned int a : 9;
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volatile unsigned int b : 1;
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unsigned int c : 1;
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} st1;
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// CIR-LAYOUT: BitFields:[
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:a offset:0 size:9 isSigned:0 storageSize:16 storageOffset:0 volatileOffset:0 volatileStorageSize:32 volatileStorageOffset:0>
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:b offset:9 size:1 isSigned:0 storageSize:16 storageOffset:0 volatileOffset:9 volatileStorageSize:32 volatileStorageOffset:0>
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:c offset:10 size:1 isSigned:0 storageSize:16 storageOffset:0 volatileOffset:10 volatileStorageSize:32 volatileStorageOffset:0>
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// OGCG-LAYOUT: BitFields:[
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:9 IsSigned:0 StorageSize:16 StorageOffset:0 VolatileOffset:0 VolatileStorageSize:32 VolatileStorageOffset:0>
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:9 Size:1 IsSigned:0 StorageSize:16 StorageOffset:0 VolatileOffset:9 VolatileStorageSize:32 VolatileStorageOffset:0>
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:10 Size:1 IsSigned:0 StorageSize:16 StorageOffset:0 VolatileOffset:10 VolatileStorageSize:32 VolatileStorageOffset:0>
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// different base types
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typedef struct{
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volatile short a : 3;
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volatile int b: 13;
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volatile long c : 5;
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} st2;
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// CIR-LAYOUT: BitFields:[
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:a offset:0 size:3 isSigned:1 storageSize:32 storageOffset:0 volatileOffset:0 volatileStorageSize:16 volatileStorageOffset:0>
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:b offset:3 size:13 isSigned:1 storageSize:32 storageOffset:0 volatileOffset:3 volatileStorageSize:32 volatileStorageOffset:0>
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:c offset:16 size:5 isSigned:1 storageSize:32 storageOffset:0 volatileOffset:16 volatileStorageSize:64 volatileStorageOffset:0>
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// OGCG-LAYOUT: BitFields:[
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:3 IsSigned:1 StorageSize:32 StorageOffset:0 VolatileOffset:0 VolatileStorageSize:16 VolatileStorageOffset:0>
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:3 Size:13 IsSigned:1 StorageSize:32 StorageOffset:0 VolatileOffset:3 VolatileStorageSize:32 VolatileStorageOffset:0>
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:16 Size:5 IsSigned:1 StorageSize:32 StorageOffset:0 VolatileOffset:16 VolatileStorageSize:64 VolatileStorageOffset:0>
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typedef struct{
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volatile unsigned int a : 3;
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unsigned int : 0; // zero-length bit-field force next field to aligned int boundary
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volatile unsigned int b : 5;
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} st3;
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// CIR-LAYOUT: BitFields:[
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:a offset:0 size:3 isSigned:0 storageSize:8 storageOffset:0 volatileOffset:0 volatileStorageSize:32 volatileStorageOffset:0>
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:b offset:0 size:5 isSigned:0 storageSize:8 storageOffset:4 volatileOffset:0 volatileStorageSize:0 volatileStorageOffset:0>
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// OGCG-LAYOUT: BitFields:[
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:3 IsSigned:0 StorageSize:8 StorageOffset:0 VolatileOffset:0 VolatileStorageSize:32 VolatileStorageOffset:0>
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:5 IsSigned:0 StorageSize:8 StorageOffset:4 VolatileOffset:0 VolatileStorageSize:0 VolatileStorageOffset:0>
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typedef struct{
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volatile unsigned int a : 3;
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unsigned int z;
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volatile unsigned long b : 16;
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} st4;
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// CIR-LAYOUT: BitFields:[
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:a offset:0 size:3 isSigned:0 storageSize:8 storageOffset:0 volatileOffset:0 volatileStorageSize:32 volatileStorageOffset:0>
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// CIR-LAYOUT-NEXT: <CIRBitFieldInfo name:b offset:0 size:16 isSigned:0 storageSize:16 storageOffset:8 volatileOffset:0 volatileStorageSize:64 volatileStorageOffset:1>
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// OGCG-LAYOUT: BitFields:[
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:3 IsSigned:0 StorageSize:8 StorageOffset:0 VolatileOffset:0 VolatileStorageSize:32 VolatileStorageOffset:0>
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// OGCG-LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:16 IsSigned:0 StorageSize:16 StorageOffset:8 VolatileOffset:0 VolatileStorageSize:64 VolatileStorageOffset:1>
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void def () {
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st1 s1;
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st2 s2;
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st3 s3;
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st4 s4;
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}
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int check_load(st1 *s1) {
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return s1->b;
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}
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// CIR: cir.func dso_local @check_load
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// CIR: [[LOAD:%.*]] = cir.load align(8) {{.*}} : !cir.ptr<!cir.ptr<!rec_st1>>, !cir.ptr<!rec_st1>
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// CIR: [[MEMBER:%.*]] = cir.get_member [[LOAD]][0] {name = "b"} : !cir.ptr<!rec_st1> -> !cir.ptr<!u16i>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(4) (#bfi_b, [[MEMBER]] {is_volatile} : !cir.ptr<!u16i>) -> !u32i
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// CIR: [[CAST:%.*]] = cir.cast(integral, [[BITFI]] : !u32i), !s32i
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// CIR: cir.store [[CAST]], [[RETVAL:%.*]] : !s32i, !cir.ptr<!s32i>
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// CIR: [[RET:%.*]] = cir.load [[RETVAL]] : !cir.ptr<!s32i>, !s32i
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// CIR: cir.return [[RET]] : !s32i
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// LLVM:define dso_local i32 @check_load
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// LLVM: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// LLVM: [[MEMBER:%.*]] = getelementptr %struct.st1, ptr [[LOAD]], i32 0, i32 0
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// LLVM: [[LOADVOL:%.*]] = load volatile i32, ptr [[MEMBER]], align 4
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// LLVM: [[LSHR:%.*]] = lshr i32 [[LOADVOL]], 9
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// LLVM: [[CLEAR:%.*]] = and i32 [[LSHR]], 1
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// LLVM: store i32 [[CLEAR]], ptr [[RETVAL:%.*]], align 4
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// LLVM: [[RET:%.*]] = load i32, ptr [[RETVAL]], align 4
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// LLVM: ret i32 [[RET]]
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// OGCG: define dso_local i32 @check_load
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// OGCG: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// OGCG: [[LOADVOL:%.*]] = load volatile i32, ptr [[LOAD]], align 4
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// OGCG: [[LSHR:%.*]] = lshr i32 [[LOADVOL]], 9
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// OGCG: [[CLEAR:%.*]] = and i32 [[LSHR]], 1
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// OGCG: ret i32 [[CLEAR]]
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// this volatile bit-field container overlaps with a zero-length bit-field,
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// so it may be accessed without using the container's width.
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int check_load_exception(st3 *s3) {
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return s3->b;
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}
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// CIR: cir.func dso_local @check_load_exception
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// CIR: [[LOAD:%.*]] = cir.load align(8) {{.*}} : !cir.ptr<!cir.ptr<!rec_st3>>, !cir.ptr<!rec_st3>
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// CIR: [[MEMBER:%.*]] = cir.get_member [[LOAD]][2] {name = "b"} : !cir.ptr<!rec_st3> -> !cir.ptr<!u8i>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(4) (#bfi_b1, [[MEMBER]] {is_volatile} : !cir.ptr<!u8i>) -> !u32i
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// CIR: [[CAST:%.*]] = cir.cast(integral, [[BITFI]] : !u32i), !s32i
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// CIR: cir.store [[CAST]], [[RETVAL:%.*]] : !s32i, !cir.ptr<!s32i>
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// CIR: [[RET:%.*]] = cir.load [[RETVAL]] : !cir.ptr<!s32i>, !s32i
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// CIR: cir.return [[RET]] : !s32i
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// LLVM:define dso_local i32 @check_load_exception
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// LLVM: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// LLVM: [[MEMBER:%.*]] = getelementptr %struct.st3, ptr [[LOAD]], i32 0, i32 2
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// LLVM: [[LOADVOL:%.*]] = load volatile i8, ptr [[MEMBER]], align 4
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// LLVM: [[CLEAR:%.*]] = and i8 [[LOADVOL]], 31
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// LLVM: [[CAST:%.*]] = zext i8 [[CLEAR]] to i32
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// LLVM: store i32 [[CAST]], ptr [[RETVAL:%.*]], align 4
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// LLVM: [[RET:%.*]] = load i32, ptr [[RETVAL]], align 4
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// LLVM: ret i32 [[RET]]
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// OGCG: define dso_local i32 @check_load_exception
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// OGCG: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// OGCG: [[MEMBER:%.*]] = getelementptr inbounds nuw %struct.st3, ptr [[LOAD]], i32 0, i32 2
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// OGCG: [[LOADVOL:%.*]] = load volatile i8, ptr [[MEMBER]], align 4
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// OGCG: [[CLEAR:%.*]] = and i8 [[LOADVOL]], 31
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// OGCG: [[CAST:%.*]] = zext i8 [[CLEAR]] to i32
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// OGCG: ret i32 [[CAST]]
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typedef struct {
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volatile int a : 24;
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char b;
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volatile int c: 30;
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} clip;
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int clip_load_exception2(clip *c) {
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return c->a;
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}
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// CIR: cir.func dso_local @clip_load_exception2
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// CIR: [[LOAD:%.*]] = cir.load align(8) {{.*}} : !cir.ptr<!cir.ptr<!rec_clip>>, !cir.ptr<!rec_clip>
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// CIR: [[MEMBER:%.*]] = cir.get_member [[LOAD]][0] {name = "a"} : !cir.ptr<!rec_clip> -> !cir.ptr<!cir.array<!u8i x 3>>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(4) (#bfi_a1, [[MEMBER]] {is_volatile} : !cir.ptr<!cir.array<!u8i x 3>>) -> !s32i
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// CIR: cir.store [[BITFI]], [[RETVAL:%.*]] : !s32i, !cir.ptr<!s32i>
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// CIR: [[RET:%.*]] = cir.load [[RETVAL]] : !cir.ptr<!s32i>, !s32i
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// CIR: cir.return [[RET]] : !s32i
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// LLVM:define dso_local i32 @clip_load_exception2
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// LLVM: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// LLVM: [[MEMBER:%.*]] = getelementptr %struct.clip, ptr [[LOAD]], i32 0, i32 0
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// LLVM: [[LOADVOL:%.*]] = load volatile i24, ptr [[MEMBER]], align 4
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// LLVM: [[CAST:%.*]] = sext i24 [[LOADVOL]] to i32
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// LLVM: store i32 [[CAST]], ptr [[RETVAL:%.*]], align 4
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// LLVM: [[RET:%.*]] = load i32, ptr [[RETVAL]], align 4
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// LLVM: ret i32 [[RET]]
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// OGCG: define dso_local i32 @clip_load_exception2
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// OGCG: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// OGCG: [[LOADVOL:%.*]] = load volatile i24, ptr [[LOAD]], align 4
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// OGCG: [[CAST:%.*]] = sext i24 [[LOADVOL]] to i32
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// OGCG: ret i32 [[CAST]]
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void check_store(st2 *s2) {
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s2->a = 1;
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}
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// CIR: cir.func dso_local @check_store
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// CIR: [[CONST:%.*]] = cir.const #cir.int<1> : !s32i
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// CIR: [[CAST:%.*]] = cir.cast(integral, [[CONST]] : !s32i), !s16i
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// CIR: [[LOAD:%.*]] = cir.load align(8) {{.*}} : !cir.ptr<!cir.ptr<!rec_st2>>, !cir.ptr<!rec_st2>
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// CIR: [[MEMBER:%.*]] = cir.get_member [[LOAD]][0] {name = "a"} : !cir.ptr<!rec_st2> -> !cir.ptr<!u32i>
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// CIR: [[SETBF:%.*]] = cir.set_bitfield align(8) (#bfi_a, [[MEMBER]] : !cir.ptr<!u32i>, [[CAST]] : !s16i) {is_volatile} -> !s16i
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// CIR: cir.return
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// LLVM:define dso_local void @check_store
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// LLVM: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// LLVM: [[MEMBER:%.*]] = getelementptr %struct.st2, ptr [[LOAD]], i32 0, i32 0
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// LLVM: [[LOADVOL:%.*]] = load volatile i16, ptr [[MEMBER]], align 8
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// LLVM: [[CLEAR:%.*]] = and i16 [[LOADVOL]], -8
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// LLVM: [[SET:%.*]] = or i16 [[CLEAR]], 1
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// LLVM: store volatile i16 [[SET]], ptr [[MEMBER]], align 8
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// LLVM: ret void
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// OGCG: define dso_local void @check_store
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// OGCG: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// OGCG: [[LOADVOL:%.*]] = load volatile i16, ptr [[LOAD]], align 8
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// OGCG: [[CLEAR:%.*]] = and i16 [[LOADVOL]], -8
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// OGCG: [[SET:%.*]] = or i16 [[CLEAR]], 1
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// OGCG: store volatile i16 [[SET]], ptr [[LOAD]], align 8
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// OGCG: ret void
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// this volatile bit-field container overlaps with a zero-length bit-field,
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// so it may be accessed without using the container's width.
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void check_store_exception(st3 *s3) {
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s3->b = 2;
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}
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// CIR: cir.func dso_local @check_store_exception
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// CIR: [[CONST:%.*]] = cir.const #cir.int<2> : !s32i
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// CIR: [[CAST:%.*]] = cir.cast(integral, [[CONST]] : !s32i), !u32i
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// CIR: [[LOAD:%.*]] = cir.load align(8) {{.*}} : !cir.ptr<!cir.ptr<!rec_st3>>, !cir.ptr<!rec_st3>
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// CIR: [[MEMBER:%.*]] = cir.get_member [[LOAD]][2] {name = "b"} : !cir.ptr<!rec_st3> -> !cir.ptr<!u8i>
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// CIR: [[SETBF:%.*]] = cir.set_bitfield align(4) (#bfi_b1, [[MEMBER]] : !cir.ptr<!u8i>, [[CAST]] : !u32i) {is_volatile} -> !u32i
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// CIR: cir.return
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// LLVM:define dso_local void @check_store_exception
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// LLVM: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// LLVM: [[MEMBER:%.*]] = getelementptr %struct.st3, ptr [[LOAD]], i32 0, i32 2
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// LLVM: [[LOADVOL:%.*]] = load volatile i8, ptr [[MEMBER]], align 4
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// LLVM: [[CLEAR:%.*]] = and i8 [[LOADVOL]], -32
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// LLVM: [[SET:%.*]] = or i8 [[CLEAR]], 2
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// LLVM: store volatile i8 [[SET]], ptr [[MEMBER]], align 4
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// LLVM: ret void
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// OGCG: define dso_local void @check_store_exception
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// OGCG: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// OGCG: [[MEMBER:%.*]] = getelementptr inbounds nuw %struct.st3, ptr [[LOAD]], i32 0, i32 2
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// OGCG: [[LOADVOL:%.*]] = load volatile i8, ptr [[MEMBER]], align 4
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// OGCG: [[CLEAR:%.*]] = and i8 [[LOADVOL]], -32
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// OGCG: [[SET:%.*]] = or i8 [[CLEAR]], 2
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// OGCG: store volatile i8 [[SET]], ptr [[MEMBER]], align 4
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// OGCG: ret void
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void clip_store_exception2(clip *c) {
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c->a = 3;
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}
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// CIR: cir.func dso_local @clip_store_exception2
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// CIR: [[CONST:%.*]] = cir.const #cir.int<3> : !s32i
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// CIR: [[LOAD:%.*]] = cir.load align(8) {{.*}} : !cir.ptr<!cir.ptr<!rec_clip>>, !cir.ptr<!rec_clip>
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// CIR: [[MEMBER:%.*]] = cir.get_member [[LOAD]][0] {name = "a"} : !cir.ptr<!rec_clip> -> !cir.ptr<!cir.array<!u8i x 3>>
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// CIR: [[SETBF:%.*]] = cir.set_bitfield align(4) (#bfi_a1, [[MEMBER]] : !cir.ptr<!cir.array<!u8i x 3>>, [[CONST]] : !s32i) {is_volatile} -> !s32i
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// CIR: cir.return
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// LLVM:define dso_local void @clip_store_exception2
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// LLVM: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// LLVM: [[MEMBER:%.*]] = getelementptr %struct.clip, ptr [[LOAD]], i32 0, i32 0
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// LLVM: store volatile i24 3, ptr [[MEMBER]], align 4
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// LLVM: ret void
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// OGCG: define dso_local void @clip_store_exception2
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// OGCG: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// OGCG: store volatile i24 3, ptr [[LOAD]], align 4
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// OGCG: ret void
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void check_store_second_member (st4 *s4) {
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s4->b = 1;
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}
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// CIR: cir.func dso_local @check_store_second_member
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// CIR: [[ONE:%.*]] = cir.const #cir.int<1> : !s32i
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// CIR: [[CAST:%.*]] = cir.cast(integral, [[ONE]] : !s32i), !u64i
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// CIR: [[LOAD:%.*]] = cir.load align(8) {{.*}} : !cir.ptr<!cir.ptr<!rec_st4>>, !cir.ptr<!rec_st4>
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// CIR: [[MEMBER:%.*]] = cir.get_member [[LOAD]][2] {name = "b"} : !cir.ptr<!rec_st4> -> !cir.ptr<!u16i>
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// CIR: cir.set_bitfield align(8) (#bfi_b2, [[MEMBER]] : !cir.ptr<!u16i>, [[CAST]] : !u64i) {is_volatile} -> !u64i
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// LLVM: define dso_local void @check_store_second_member
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// LLVM: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// LLVM: [[MEMBER:%.*]] = getelementptr %struct.st4, ptr [[LOAD]], i32 0, i32 2
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// LLVM: [[VAL:%.*]] = load volatile i64, ptr [[MEMBER]], align 8
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// LLVM: [[CLEAR:%.*]] = and i64 [[VAL]], -65536
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// LLVM: [[SET:%.*]] = or i64 [[CLEAR]], 1
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// LLVM: store volatile i64 [[SET]], ptr [[MEMBER]], align 8
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// OGCG: define dso_local void @check_store_second_member
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// OGCG: [[LOAD:%.*]] = load ptr, ptr {{.*}}, align 8
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// OGCG: [[MEMBER:%.*]] = getelementptr inbounds i64, ptr [[LOAD]], i64 1
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// OGCG: [[LOADBF:%.*]] = load volatile i64, ptr [[MEMBER]], align 8
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// OGCG: [[CLR:%.*]] = and i64 [[LOADBF]], -65536
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// OGCG: [[SET:%.*]] = or i64 [[CLR]], 1
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// OGCG: store volatile i64 [[SET]], ptr [[MEMBER]], align 8
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