ea9046699e
For function whose vscale_range is limited to a single value we can size scalable vectors. This aids SROA by allowing scalable vector load and store operations to be considered for replacement whereby bitcasts through memory can be replaced by vector insert or extract operations.
111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -mvscale-min=4 -mvscale-max=4 -O1 -emit-llvm -o - %s | FileCheck %s
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// REQUIRES: aarch64-registered-target
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#include <arm_sve.h>
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#define N __ARM_FEATURE_SVE_BITS
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typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
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typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
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typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
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typedef int32_t gnu_int32_t __attribute__((vector_size(N / 8)));
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// CHECK-LABEL: @to_svint32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TYPE_COERCE:%.*]]
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//
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svint32_t to_svint32_t(fixed_int32_t type) {
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return type;
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}
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// CHECK-LABEL: @from_svint32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TYPE:%.*]]
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//
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fixed_int32_t from_svint32_t(svint32_t type) {
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return type;
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}
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// CHECK-LABEL: @to_svfloat64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 2 x double> [[TYPE_COERCE:%.*]]
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//
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svfloat64_t to_svfloat64_t(fixed_float64_t type) {
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return type;
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}
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// CHECK-LABEL: @from_svfloat64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 2 x double> [[TYPE:%.*]]
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//
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fixed_float64_t from_svfloat64_t(svfloat64_t type) {
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return type;
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}
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// CHECK-LABEL: @to_svbool_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0:%.*]]
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//
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svbool_t to_svbool_t(fixed_bool_t type) {
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return type;
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}
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// CHECK-LABEL: @from_svbool_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TYPE:%.*]]
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//
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fixed_bool_t from_svbool_t(svbool_t type) {
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return type;
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}
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// CHECK-LABEL: @lax_cast(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[TYPE_COERCE:%.*]] to <vscale x 2 x i64>
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// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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svint64_t lax_cast(fixed_int32_t type) {
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return type;
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}
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// CHECK-LABEL: @to_svint32_t__from_gnu_int32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TYPE:%.*]] = load <16 x i32>, ptr [[TMP0:%.*]], align 16, !tbaa [[TBAA2:![0-9]+]]
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// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> [[TYPE]], i64 0)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[CAST_SCALABLE]]
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//
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svint32_t to_svint32_t__from_gnu_int32_t(gnu_int32_t type) {
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return type;
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}
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// CHECK-LABEL: @from_svint32_t__to_gnu_int32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CAST_FIXED:%.*]] = tail call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE:%.*]], i64 0)
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// CHECK-NEXT: store <16 x i32> [[CAST_FIXED]], ptr [[AGG_RESULT:%.*]], align 16, !tbaa [[TBAA2]]
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// CHECK-NEXT: ret void
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//
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gnu_int32_t from_svint32_t__to_gnu_int32_t(svint32_t type) {
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return type;
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}
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// CHECK-LABEL: @to_fixed_int32_t__from_gnu_int32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TYPE:%.*]] = load <16 x i32>, ptr [[TMP0:%.*]], align 16, !tbaa [[TBAA2]]
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// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> poison, <16 x i32> [[TYPE]], i64 0)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[CAST_SCALABLE]]
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//
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fixed_int32_t to_fixed_int32_t__from_gnu_int32_t(gnu_int32_t type) {
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return type;
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}
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// CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TYPE:%.*]] = tail call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[TYPE_COERCE:%.*]], i64 0)
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// CHECK-NEXT: store <16 x i32> [[TYPE]], ptr [[AGG_RESULT:%.*]], align 16, !tbaa [[TBAA2]]
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// CHECK-NEXT: ret void
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//
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gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) {
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return type;
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}
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