a0c2d6e369
I've wanted a utility to create a corefile for test purposes given a bit
of memory and regsters, for a while. I've written a few API tests over
the years that needed exactly this capability -- we have several one-off
Mach-O corefile creator utility in the API testsuite to do this. But
it's a lot of boilerplate when you only want to specify some register
contents and memory contents, to create an API test.
This adds yaml2mach-core, a tool that should build on any system, takes
a yaml description of register values for one or more threads,
optionally memory values for one or more memory regions, and can take a
list of UUIDs that will be added as LC_NOTE "load binary" metadata to
the corefile so binaries can be loaded into virtual address space in a
test scenario.
The format of the yaml file looks like
```
cpu: armv7m
# optionally specify the number of bits used for addressing
# (this line is from a different, 64-bit, yaml file)
addressable-bits:
num-bits: 39
# optionally specify one or more binary UUID and slide/virtual address to be added as an LC_NOTE
# (this line is from a different, 64-bit, yaml file)
binaries:
- name: debug-binary.development
uuid: 67942352-5857-3D3D-90CB-A3F80BA67B04
virtual-address: 0xfffffff01840c000
threads:
- regsets:
- flavor: gpr
registers: [{name: sp, value: 0x2000fe70}, {name: r7, value: 0x2000fe80},
{name: pc, value: 0x0020392c}, {name: lr, value: 0x0020392d}]
memory-regions:
# stack memory
- addr: 0x2000fe70
UInt32: [ 0x0000002a, 0x20010e58, 0x00203923,
0x00000001, 0x2000fe88, 0x00203911,
0x2000ffdc, 0xfffffff9 ]
# instructions of a function
- addr: 0x203910
UInt8: [ 0xf8, 0xb5, 0x04, 0xaf, 0x06, 0x4c, 0x07, 0x49,
0x74, 0xf0, 0x2e, 0xf8, 0x01, 0xac, 0x74, 0xf0 ]
```
and that's all that is needed to specify a corefile where four register
values are specified (the others will be set to 0), and two memory
regions will be emitted.
The memory can be specified as an array of UInt8, UInt32, or UInt64, I
anticipate that some of these corefiles may have stack values
constructed manually and it may be simpler for a human to write them in
a particular grouping of values.
I needed this utility for an upcoming patch for ARM Cortex-M processors,
to create a test for the change. I took the opportunity to remove two of
the "trivial mach-o corefile" creator utilities I've written in the
past, which also restricted the tests to only run on Darwin systems
because I was using the system headers for Mach-O constant values.
rdar://110663219
201 lines
8.0 KiB
C++
201 lines
8.0 KiB
C++
//===-- ThreadWriter.cpp --------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ThreadWriter.h"
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#include "CoreSpec.h"
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#include "Utility.h"
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#include "llvm/BinaryFormat/MachO.h"
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#include <algorithm>
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#include <stdio.h>
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#define ARM_THREAD_STATE 1
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#define ARM_THREAD_STATE_COUNT 17
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#define ARM_EXCEPTION_STATE 3
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#define ARM_EXCEPTION_STATE_COUNT 3
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std::vector<RegisterNameAndValue>::const_iterator
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find_by_name(std::vector<RegisterNameAndValue>::const_iterator first,
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std::vector<RegisterNameAndValue>::const_iterator last,
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const char *name) {
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for (; first != last; ++first)
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if (first->name == name)
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return first;
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return last;
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}
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void add_reg_value(CoreSpec &spec, std::vector<uint8_t> &buf,
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const std::vector<RegisterNameAndValue> ®isters,
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const char *regname, int regsize) {
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const auto it = find_by_name(registers.begin(), registers.end(), regname);
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if (it != registers.end()) {
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if (regsize == 8)
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add_uint64(buf, it->value);
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else
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add_uint32(buf, it->value);
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} else {
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if (regsize == 8)
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add_uint64(buf, 0);
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else
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add_uint32(buf, 0);
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}
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}
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void add_reg_value_32(CoreSpec &spec, std::vector<uint8_t> &buf,
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const std::vector<RegisterNameAndValue> ®isters,
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const char *regname) {
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add_reg_value(spec, buf, registers, regname, 4);
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}
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void add_reg_value_64(CoreSpec &spec, std::vector<uint8_t> &buf,
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const std::vector<RegisterNameAndValue> ®isters,
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const char *regname) {
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add_reg_value(spec, buf, registers, regname, 8);
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}
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void add_lc_threads_armv7(CoreSpec &spec,
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std::vector<std::vector<uint8_t>> &load_commands) {
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for (const Thread &th : spec.threads) {
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std::vector<uint8_t> lc;
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int size_of_all_flavors = 0;
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for (const RegisterSet &rs : th.regsets) {
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if (rs.flavor == RegisterFlavor::GPR)
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size_of_all_flavors += (ARM_THREAD_STATE_COUNT * 4);
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if (rs.flavor == RegisterFlavor::EXC)
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size_of_all_flavors += (ARM_EXCEPTION_STATE_COUNT * 4);
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}
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int cmdsize = 4 * 2; // cmd, cmdsize
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cmdsize += 4 * 2 * th.regsets.size(); // flavor, count (per register flavor)
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cmdsize += size_of_all_flavors; // size of all the register set data
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add_uint32(lc, llvm::MachO::LC_THREAD); // thread_command.cmd
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add_uint32(lc, cmdsize); // thread_command.cmdsize
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for (const RegisterSet &rs : th.regsets) {
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if (rs.flavor == RegisterFlavor::GPR) {
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add_uint32(lc, ARM_THREAD_STATE); // thread_command.flavor
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add_uint32(lc, ARM_THREAD_STATE_COUNT); // thread_command.count
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const char *names[] = {"r0", "r1", "r2", "r3", "r4", "r5",
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"r6", "r7", "r8", "r9", "r10", "r11",
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"r12", "sp", "lr", "pc", "cpsr", nullptr};
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for (int i = 0; names[i]; i++)
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add_reg_value_32(spec, lc, rs.registers, names[i]);
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}
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if (rs.flavor == RegisterFlavor::EXC) {
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add_uint32(lc, ARM_EXCEPTION_STATE); // thread_command.flavor
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add_uint32(lc, ARM_EXCEPTION_STATE_COUNT); // thread_command.count
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const char *names[] = {"far", "esr", "exception", nullptr};
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for (int i = 0; names[i]; i++)
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add_reg_value_32(spec, lc, rs.registers, names[i]);
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}
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}
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load_commands.push_back(lc);
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}
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}
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#define ARM_THREAD_STATE64 6
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#define ARM_THREAD_STATE64_COUNT 68
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#define ARM_EXCEPTION_STATE64 7
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#define ARM_EXCEPTION_STATE64_COUNT 4
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void add_lc_threads_arm64(CoreSpec &spec,
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std::vector<std::vector<uint8_t>> &load_commands) {
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for (const Thread &th : spec.threads) {
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std::vector<uint8_t> lc;
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int size_of_all_flavors = 0;
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for (const RegisterSet &rs : th.regsets) {
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if (rs.flavor == RegisterFlavor::GPR)
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size_of_all_flavors += (ARM_THREAD_STATE64_COUNT * 4);
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if (rs.flavor == RegisterFlavor::EXC)
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size_of_all_flavors += (ARM_EXCEPTION_STATE64_COUNT * 4);
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}
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int cmdsize = 4 * 2; // cmd, cmdsize
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cmdsize += 4 * 2 * th.regsets.size(); // flavor, count (per register flavor)
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cmdsize += size_of_all_flavors; // size of all the register set data
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add_uint32(lc, llvm::MachO::LC_THREAD); // thread_command.cmd
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add_uint32(lc, cmdsize); // thread_command.cmdsize
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for (const RegisterSet &rs : th.regsets) {
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if (rs.flavor == RegisterFlavor::GPR) {
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add_uint32(lc, ARM_THREAD_STATE64); // thread_command.flavor
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add_uint32(lc, ARM_THREAD_STATE64_COUNT); // thread_command.count
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const char *names[] = {"x0", "x1", "x2", "x3", "x4", "x5", "x6",
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"x7", "x8", "x9", "x10", "x11", "x12", "x13",
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"x14", "x15", "x16", "x17", "x18", "x19", "x20",
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"x21", "x22", "x23", "x24", "x25", "x26", "x27",
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"x28", "fp", "lr", "sp", "pc", nullptr};
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for (int i = 0; names[i]; i++)
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add_reg_value_64(spec, lc, rs.registers, names[i]);
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// cpsr is a 4-byte reg
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add_reg_value_32(spec, lc, rs.registers, "cpsr");
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// the 4 bytes of zeroes
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add_uint32(lc, 0);
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}
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if (rs.flavor == RegisterFlavor::EXC) {
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add_uint32(lc, ARM_EXCEPTION_STATE64); // thread_command.flavor
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add_uint32(lc,
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ARM_EXCEPTION_STATE64_COUNT); // thread_command.count
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add_reg_value_64(spec, lc, rs.registers, "far");
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add_reg_value_32(spec, lc, rs.registers, "esr");
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add_reg_value_32(spec, lc, rs.registers, "exception");
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}
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}
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load_commands.push_back(lc);
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}
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}
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#define RV32_THREAD_STATE 2
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#define RV32_THREAD_STATE_COUNT 33
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void add_lc_threads_riscv(CoreSpec &spec,
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std::vector<std::vector<uint8_t>> &load_commands) {
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for (const Thread &th : spec.threads) {
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std::vector<uint8_t> lc;
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int size_of_all_flavors = 0;
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for (const RegisterSet &rs : th.regsets) {
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if (rs.flavor == RegisterFlavor::GPR)
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size_of_all_flavors += (RV32_THREAD_STATE_COUNT * 4);
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}
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int cmdsize = 4 * 2; // cmd, cmdsize
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cmdsize += 4 * 2 * th.regsets.size(); // flavor, count (per register flavor)
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cmdsize += size_of_all_flavors; // size of all the register set data
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add_uint32(lc, llvm::MachO::LC_THREAD); // thread_command.cmd
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add_uint32(lc, cmdsize); // thread_command.cmdsize
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for (const RegisterSet &rs : th.regsets) {
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if (rs.flavor == RegisterFlavor::GPR) {
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add_uint32(lc, RV32_THREAD_STATE); // thread_command.flavor
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add_uint32(lc, RV32_THREAD_STATE_COUNT); // thread_command.count
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const char *names[] = {"zero", "ra", "sp", "gp", "tp", "t0", "t1",
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"t2", "fp", "s1", "a0", "a1", "a2", "a3",
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"a4", "a5", "a6", "a7", "s2", "s3", "s4",
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"s5", "s6", "s7", "s8", "s9", "s10", "s11",
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"t3", "t4", "t5", "t6", "pc", nullptr};
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for (int i = 0; names[i]; i++)
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add_reg_value_32(spec, lc, rs.registers, names[i]);
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}
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}
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load_commands.push_back(lc);
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}
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}
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void add_lc_threads(CoreSpec &spec,
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std::vector<std::vector<uint8_t>> &load_commands) {
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if (spec.cputype == llvm::MachO::CPU_TYPE_ARM)
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add_lc_threads_armv7(spec, load_commands);
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else if (spec.cputype == llvm::MachO::CPU_TYPE_ARM64)
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add_lc_threads_arm64(spec, load_commands);
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else if (spec.cputype == llvm::MachO::CPU_TYPE_RISCV)
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add_lc_threads_riscv(spec, load_commands);
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else {
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fprintf(stderr,
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"Unrecognized cputype, could not write LC_THREAD. Exiting.\n");
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exit(1);
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}
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}
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