056e5a32c8
Keep bf16/f16 values encoded as the low half of a 32-bit register, instead of promoting to float. This avoids unwanted FP effects from the fpext/fptrunc which should not be implied by just passing an argument. This also fixes ABI divergence between SelectionDAG and GlobalISel. I've wanted to make this change for ages, and failed the last few times. The main complication was the hack to return shader integer types in SGPRs, which now needs to inspect the underlying IR type.
200 lines
6.7 KiB
TableGen
200 lines
6.7 KiB
TableGen
//===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the AMD Radeon GPUs.
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//
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//===----------------------------------------------------------------------===//
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// Inversion of CCIfInReg
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class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
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class CCIfExtend<CCAction A>
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: CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
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class CCIfOrigTypeShaderCCIsSGPR<CCAction A>
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: CCIf<[{(!OrigTy->getScalarType()->isFloatTy() &&
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!OrigTy->getScalarType()->isHalfTy()) }], A>;
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// Calling convention for SI
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def CC_SI_Gfx : CallingConv<[
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// 0-3 are reserved for the stack buffer descriptor
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// 30-31 are reserved for the return address
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// 32 is reserved for the stack pointer
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// 33 is reserved for the frame pointer
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// 34 is reserved for the base pointer
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CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(4, 30), !cast<Register>("SGPR"#i)) // SGPR4-29
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>>>,
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
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>>>,
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CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
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]>;
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def RetCC_SI_Gfx : CallingConv<[
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CCIfType<[i1], CCPromoteToType<i32>>,
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CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
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>>>,
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]>;
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def CC_SI_SHADER : CallingConv<[
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CCIfType<[i1], CCPromoteToType<i32>>,
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CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(0, 44), !cast<Register>("SGPR"#i)) // SGPR0-43
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>>>,
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// 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
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>>>
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]>;
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def RetCC_SI_Shader : CallingConv<[
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CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfType<[i32, i16, v2i16], CCIfOrigTypeShaderCCIsSGPR<CCAssignToReg<
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!foreach(i, !range(0, 44), !cast<Register>("SGPR"#i)) // SGPR0-43
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>>>,
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// 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
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CCIfType<[f32, f16, v2f16, bf16, v2bf16, i32, i16, v2i16] , CCAssignToReg<
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!foreach(i, !range(0, 136), !cast<Register>("VGPR"#i)) // VGPR0-135
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>>
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]>;
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def CSR_AMDGPU_VGPRs : CalleeSavedRegs<
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// The CSRs & scratch-registers are interleaved at a split boundary of 8.
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(add (sequence "VGPR%u", 40, 47),
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(sequence "VGPR%u", 56, 63),
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(sequence "VGPR%u", 72, 79),
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(sequence "VGPR%u", 88, 95),
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(sequence "VGPR%u", 104, 111),
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(sequence "VGPR%u", 120, 127),
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(sequence "VGPR%u", 136, 143),
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(sequence "VGPR%u", 152, 159),
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(sequence "VGPR%u", 168, 175),
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(sequence "VGPR%u", 184, 191),
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(sequence "VGPR%u", 200, 207),
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(sequence "VGPR%u", 216, 223),
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(sequence "VGPR%u", 232, 239),
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(sequence "VGPR%u", 248, 255))
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>;
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def CSR_AMDGPU_AGPRs : CalleeSavedRegs<
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(sequence "AGPR%u", 32, 255)
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>;
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def CSR_AMDGPU_SGPRs : CalleeSavedRegs<
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// Ensure that s30-s31 (return address), s32 (stack pointer), s33 (frame pointer),
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// and s34 (base pointer) are callee-saved. The striped layout starts from s40,
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// with a stripe width of 8. The last stripe is 10 wide instead of 8, to avoid
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// ending with a 2-wide stripe.
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(add (sequence "SGPR%u", 30, 39),
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(sequence "SGPR%u", 48, 55),
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(sequence "SGPR%u", 64, 71),
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(sequence "SGPR%u", 80, 87),
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(sequence "SGPR%u", 96, 105))
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>;
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def CSR_AMDGPU_SI_Gfx_SGPRs : CalleeSavedRegs<
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(add (sequence "SGPR%u", 4, 31), (sequence "SGPR%u", 64, 105))
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>;
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def CSR_AMDGPU : CalleeSavedRegs<
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(add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs)
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>;
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def CSR_AMDGPU_GFX90AInsts : CalleeSavedRegs<
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(add CSR_AMDGPU, CSR_AMDGPU_AGPRs)
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>;
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def CSR_AMDGPU_SI_Gfx : CalleeSavedRegs<
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(add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SI_Gfx_SGPRs)
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>;
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def CSR_AMDGPU_SI_Gfx_GFX90AInsts : CalleeSavedRegs<
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(add CSR_AMDGPU_SI_Gfx, CSR_AMDGPU_AGPRs)
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>;
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def CSR_AMDGPU_CS_ChainPreserve : CalleeSavedRegs<
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(sequence "VGPR%u", 8, 255)
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>;
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def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
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// Calling convention for leaf functions
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def CC_AMDGPU_Func : CallingConv<[
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CCIfByVal<CCPassByVal<4, 4>>,
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CCIfType<[i1], CCPromoteToType<i32>>,
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CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
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>>>,
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CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<
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!foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
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>>,
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CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
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]>;
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// Calling convention for leaf functions
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def RetCC_AMDGPU_Func : CallingConv<[
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CCIfType<[i1], CCPromoteToType<i32>>,
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CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
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CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg<
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!foreach(i, !range(0, 32), !cast<Register>("VGPR"#i)) // VGPR0-31
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>>,
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]>;
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def CC_AMDGPU : CallingConv<[
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CCIf<"State.getMachineFunction().getSubtarget<GCNSubtarget>().getGeneration() >= "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS",
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CCDelegateTo<CC_SI_SHADER>>,
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CCIf<"State.getMachineFunction().getSubtarget<GCNSubtarget>().getGeneration() >= "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C",
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CCDelegateTo<CC_AMDGPU_Func>>
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]>;
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def CC_AMDGPU_CS_CHAIN : CallingConv<[
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CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(105), !cast<Register>("SGPR"#i))
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>>>,
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CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
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!foreach(i, !range(8, 255), !cast<Register>("VGPR"#i))
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>>>
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]>;
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// Trivial class to denote when a def is used only to get a RegMask, i.e.
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// SaveList is ignored and the def is not used as part of any calling
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// convention.
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class RegMask<dag mask> : CalleeSavedRegs<mask>;
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def AMDGPU_AllVGPRs : RegMask<
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(sequence "VGPR%u", 0, 255)
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>;
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def AMDGPU_AllAGPRs : RegMask<
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(sequence "AGPR%u", 0, 255)
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>;
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def AMDGPU_AllVectorRegs : RegMask<
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(add AMDGPU_AllVGPRs, AMDGPU_AllAGPRs)
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>;
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def AMDGPU_AllAllocatableSRegs : RegMask<
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(add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
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>;
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