49f4232a7d
The instruction was accidentally added, remove it. Rename OrN2Op to OrN2Opc for consistency with other names
92 lines
3.6 KiB
C++
92 lines
3.6 KiB
C++
//===- AMDGPULaneMaskUtils.h - Exec/lane mask helper functions -*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPULANEMASKUTILS_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPULANEMASKUTILS_H
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#include "GCNSubtarget.h"
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#include "llvm/CodeGen/Register.h"
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namespace llvm {
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class GCNSubtarget;
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namespace AMDGPU {
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class LaneMaskConstants {
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public:
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const Register ExecReg;
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const Register VccReg;
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const unsigned AndOpc;
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const unsigned AndTermOpc;
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const unsigned AndN2Opc;
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const unsigned AndN2SaveExecOpc;
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const unsigned AndN2TermOpc;
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const unsigned AndSaveExecOpc;
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const unsigned AndSaveExecTermOpc;
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const unsigned BfmOpc;
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const unsigned CMovOpc;
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const unsigned CSelectOpc;
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const unsigned MovOpc;
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const unsigned MovTermOpc;
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const unsigned OrOpc;
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const unsigned OrN2Opc;
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const unsigned OrTermOpc;
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const unsigned OrSaveExecOpc;
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const unsigned XorOpc;
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const unsigned XorTermOpc;
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const unsigned WQMOpc;
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constexpr LaneMaskConstants(bool IsWave32)
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: ExecReg(IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC),
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VccReg(IsWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC),
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AndOpc(IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64),
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AndTermOpc(IsWave32 ? AMDGPU::S_AND_B32_term : AMDGPU::S_AND_B64_term),
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AndN2Opc(IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64),
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AndN2SaveExecOpc(IsWave32 ? AMDGPU::S_ANDN2_SAVEEXEC_B32
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: AMDGPU::S_ANDN2_SAVEEXEC_B64),
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AndN2TermOpc(IsWave32 ? AMDGPU::S_ANDN2_B32_term
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: AMDGPU::S_ANDN2_B64_term),
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AndSaveExecOpc(IsWave32 ? AMDGPU::S_AND_SAVEEXEC_B32
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: AMDGPU::S_AND_SAVEEXEC_B64),
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AndSaveExecTermOpc(IsWave32 ? AMDGPU::S_AND_SAVEEXEC_B32_term
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: AMDGPU::S_AND_SAVEEXEC_B64_term),
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BfmOpc(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
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CMovOpc(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
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CSelectOpc(IsWave32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64),
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MovOpc(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64),
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MovTermOpc(IsWave32 ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term),
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OrOpc(IsWave32 ? AMDGPU::S_OR_B32 : AMDGPU::S_OR_B64),
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OrN2Opc(IsWave32 ? AMDGPU::S_ORN2_B32 : AMDGPU::S_ORN2_B64),
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OrTermOpc(IsWave32 ? AMDGPU::S_OR_B32_term : AMDGPU::S_OR_B64_term),
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OrSaveExecOpc(IsWave32 ? AMDGPU::S_OR_SAVEEXEC_B32
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: AMDGPU::S_OR_SAVEEXEC_B64),
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XorOpc(IsWave32 ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64),
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XorTermOpc(IsWave32 ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term),
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WQMOpc(IsWave32 ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64) {}
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static inline const LaneMaskConstants &get(const GCNSubtarget &ST);
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};
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static constexpr LaneMaskConstants LaneMaskConstants32 =
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LaneMaskConstants(/*IsWave32=*/true);
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static constexpr LaneMaskConstants LaneMaskConstants64 =
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LaneMaskConstants(/*IsWave32=*/false);
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inline const LaneMaskConstants &LaneMaskConstants::get(const GCNSubtarget &ST) {
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unsigned WavefrontSize = ST.getWavefrontSize();
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assert(WavefrontSize == 32 || WavefrontSize == 64);
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return WavefrontSize == 32 ? LaneMaskConstants32 : LaneMaskConstants64;
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}
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPULANEMASKUTILS_H
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