900c517919
This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. Autogenerated node names start with "AMDGPUISD::", hence the changes in the tests. The few nodes defined in R600.td are *not* imported because TableGen processes AMDGPU.td that doesn't include R600.td. Ideally, we would have two sets of nodes, but that would require careful reorganization of td files since some nodes are shared between AMDGPU/R600. Not sure if it something worth looking into. Some nodes fail validation, those are listed in `AMDGPUSelectionDAGInfo::verifyTargetNode()`. Part of #119709. Pull Request: https://github.com/llvm/llvm-project/pull/168248
60 lines
2.0 KiB
C++
60 lines
2.0 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUSelectionDAGInfo.h"
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#define GET_SDNODE_DESC
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#include "AMDGPUGenSDNodeInfo.inc"
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using namespace llvm;
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AMDGPUSelectionDAGInfo::AMDGPUSelectionDAGInfo()
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: SelectionDAGGenTargetInfo(AMDGPUGenSDNodeInfo) {}
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AMDGPUSelectionDAGInfo::~AMDGPUSelectionDAGInfo() = default;
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const char *AMDGPUSelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
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#define NODE_NAME_CASE(node) \
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case AMDGPUISD::node: \
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return "AMDGPUISD::" #node;
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switch (static_cast<AMDGPUISD::NodeType>(Opcode)) {
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// These nodes don't have corresponding entries in *.td files yet.
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NODE_NAME_CASE(WAVE_ADDRESS)
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NODE_NAME_CASE(MAD_I64_I32)
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NODE_NAME_CASE(MAD_U64_U32)
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NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
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// These do, but only when compiling R600.td,
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// and the enum is generated from AMDGPU.td.
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NODE_NAME_CASE(DOT4)
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NODE_NAME_CASE(TEXTURE_FETCH)
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NODE_NAME_CASE(R600_EXPORT)
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NODE_NAME_CASE(CONST_ADDRESS)
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NODE_NAME_CASE(DUMMY_CHAIN)
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}
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#undef NODE_NAME_CASE
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return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
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}
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void AMDGPUSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
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const SDNode *N) const {
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switch (N->getOpcode()) {
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case AMDGPUISD::IF:
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// result #0 must have type i1, but has type i32/i64
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case AMDGPUISD::ELSE:
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case AMDGPUISD::LOOP:
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// operand #1 must have type i1, but has type i32/i64
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case AMDGPUISD::LDS:
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// result #0 must have type i64 (iPTR), but has type i32
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return;
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}
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SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
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}
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