864 lines
29 KiB
C++
864 lines
29 KiB
C++
//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInstrInfo.h"
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#include "Sparc.h"
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#include "SparcMachineFunctionInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "SparcGenInstrInfo.inc"
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static cl::opt<unsigned> BPccDisplacementBits(
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"sparc-bpcc-offset-bits", cl::Hidden, cl::init(19),
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cl::desc("Restrict range of BPcc/FBPfcc instructions (DEBUG)"));
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static cl::opt<unsigned>
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BPrDisplacementBits("sparc-bpr-offset-bits", cl::Hidden, cl::init(16),
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cl::desc("Restrict range of BPr instructions (DEBUG)"));
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// Pin the vtable to this file.
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void SparcInstrInfo::anchor() {}
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SparcInstrInfo::SparcInstrInfo(const SparcSubtarget &ST)
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: SparcGenInstrInfo(ST, RI, SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
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RI(ST), Subtarget(ST) {}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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Register SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex,
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TypeSize &MemBytes) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case SP::LDri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::LDXri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::LDFri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::LDDFri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::LDQFri:
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MemBytes = TypeSize::getFixed(16);
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break;
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}
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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Register SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex,
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TypeSize &MemBytes) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case SP::STri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::STXri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::STFri:
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MemBytes = TypeSize::getFixed(4);
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break;
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case SP::STDFri:
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MemBytes = TypeSize::getFixed(8);
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break;
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case SP::STQFri:
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MemBytes = TypeSize::getFixed(16);
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break;
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}
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if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
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MI.getOperand(1).getImm() == 0) {
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FrameIndex = MI.getOperand(0).getIndex();
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return MI.getOperand(2).getReg();
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}
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return 0;
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}
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static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
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{
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switch(CC) {
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case SPCC::ICC_A: return SPCC::ICC_N;
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case SPCC::ICC_N: return SPCC::ICC_A;
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case SPCC::ICC_NE: return SPCC::ICC_E;
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case SPCC::ICC_E: return SPCC::ICC_NE;
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case SPCC::ICC_G: return SPCC::ICC_LE;
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case SPCC::ICC_LE: return SPCC::ICC_G;
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case SPCC::ICC_GE: return SPCC::ICC_L;
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case SPCC::ICC_L: return SPCC::ICC_GE;
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case SPCC::ICC_GU: return SPCC::ICC_LEU;
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case SPCC::ICC_LEU: return SPCC::ICC_GU;
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case SPCC::ICC_CC: return SPCC::ICC_CS;
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case SPCC::ICC_CS: return SPCC::ICC_CC;
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case SPCC::ICC_POS: return SPCC::ICC_NEG;
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case SPCC::ICC_NEG: return SPCC::ICC_POS;
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case SPCC::ICC_VC: return SPCC::ICC_VS;
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case SPCC::ICC_VS: return SPCC::ICC_VC;
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case SPCC::FCC_A: return SPCC::FCC_N;
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case SPCC::FCC_N: return SPCC::FCC_A;
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case SPCC::FCC_U: return SPCC::FCC_O;
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case SPCC::FCC_O: return SPCC::FCC_U;
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case SPCC::FCC_G: return SPCC::FCC_ULE;
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case SPCC::FCC_LE: return SPCC::FCC_UG;
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case SPCC::FCC_UG: return SPCC::FCC_LE;
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case SPCC::FCC_ULE: return SPCC::FCC_G;
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case SPCC::FCC_L: return SPCC::FCC_UGE;
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case SPCC::FCC_GE: return SPCC::FCC_UL;
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case SPCC::FCC_UL: return SPCC::FCC_GE;
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case SPCC::FCC_UGE: return SPCC::FCC_L;
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case SPCC::FCC_LG: return SPCC::FCC_UE;
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case SPCC::FCC_UE: return SPCC::FCC_LG;
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case SPCC::FCC_NE: return SPCC::FCC_E;
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case SPCC::FCC_E: return SPCC::FCC_NE;
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case SPCC::CPCC_A: return SPCC::CPCC_N;
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case SPCC::CPCC_N: return SPCC::CPCC_A;
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case SPCC::CPCC_3: [[fallthrough]];
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case SPCC::CPCC_2: [[fallthrough]];
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case SPCC::CPCC_23: [[fallthrough]];
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case SPCC::CPCC_1: [[fallthrough]];
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case SPCC::CPCC_13: [[fallthrough]];
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case SPCC::CPCC_12: [[fallthrough]];
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case SPCC::CPCC_123: [[fallthrough]];
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case SPCC::CPCC_0: [[fallthrough]];
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case SPCC::CPCC_03: [[fallthrough]];
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case SPCC::CPCC_02: [[fallthrough]];
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case SPCC::CPCC_023: [[fallthrough]];
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case SPCC::CPCC_01: [[fallthrough]];
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case SPCC::CPCC_013: [[fallthrough]];
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case SPCC::CPCC_012:
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// "Opposite" code is not meaningful, as we don't know
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// what the CoProc condition means here. The cond-code will
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// only be used in inline assembler, so this code should
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// not be reached in a normal compilation pass.
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llvm_unreachable("Meaningless inversion of co-processor cond code");
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case SPCC::REG_BEGIN:
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llvm_unreachable("Use of reserved cond code");
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case SPCC::REG_Z:
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return SPCC::REG_NZ;
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case SPCC::REG_LEZ:
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return SPCC::REG_GZ;
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case SPCC::REG_LZ:
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return SPCC::REG_GEZ;
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case SPCC::REG_NZ:
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return SPCC::REG_Z;
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case SPCC::REG_GZ:
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return SPCC::REG_LEZ;
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case SPCC::REG_GEZ:
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return SPCC::REG_LZ;
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}
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llvm_unreachable("Invalid cond code");
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}
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static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; }
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static bool isI32CondBranchOpcode(int Opc) {
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return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA ||
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Opc == SP::BPICCNT || Opc == SP::BPICCANT;
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}
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static bool isI64CondBranchOpcode(int Opc) {
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return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT ||
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Opc == SP::BPXCCANT;
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}
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static bool isRegCondBranchOpcode(int Opc) {
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return Opc == SP::BPR || Opc == SP::BPRA || Opc == SP::BPRNT ||
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Opc == SP::BPRANT;
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}
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static bool isFCondBranchOpcode(int Opc) {
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return Opc == SP::FBCOND || Opc == SP::FBCONDA || Opc == SP::FBCOND_V9 ||
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Opc == SP::FBCONDA_V9;
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}
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static bool isCondBranchOpcode(int Opc) {
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return isI32CondBranchOpcode(Opc) || isI64CondBranchOpcode(Opc) ||
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isRegCondBranchOpcode(Opc) || isFCondBranchOpcode(Opc);
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}
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static bool isIndirectBranchOpcode(int Opc) {
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return Opc == SP::BINDrr || Opc == SP::BINDri;
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}
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static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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unsigned Opc = LastInst->getOpcode();
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int64_t CC = LastInst->getOperand(1).getImm();
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// Push the branch opcode into Cond too so later in insertBranch
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// it can use the information to emit the correct SPARC branch opcode.
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Cond.push_back(MachineOperand::CreateImm(Opc));
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Cond.push_back(MachineOperand::CreateImm(CC));
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// Branch on register contents need another argument to indicate
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// the register it branches on.
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if (isRegCondBranchOpcode(Opc)) {
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Register Reg = LastInst->getOperand(2).getReg();
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Cond.push_back(MachineOperand::CreateReg(Reg, false));
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}
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Target = LastInst->getOperand(0).getMBB();
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}
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MachineBasicBlock *
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SparcInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("unexpected opcode!");
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case SP::BA:
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case SP::BCOND:
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case SP::BCONDA:
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case SP::FBCOND:
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case SP::FBCONDA:
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case SP::BPICC:
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case SP::BPICCA:
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case SP::BPICCNT:
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case SP::BPICCANT:
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case SP::BPXCC:
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case SP::BPXCCA:
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case SP::BPXCCNT:
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case SP::BPXCCANT:
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case SP::BPFCC:
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case SP::BPFCCA:
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case SP::BPFCCNT:
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case SP::BPFCCANT:
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case SP::FBCOND_V9:
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case SP::FBCONDA_V9:
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case SP::BPR:
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case SP::BPRA:
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case SP::BPRNT:
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case SP::BPRANT:
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return MI.getOperand(0).getMBB();
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}
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}
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bool SparcInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return false;
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if (!isUnpredicatedTerminator(*I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = &*I;
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unsigned LastOpc = LastInst->getOpcode();
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
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if (isUncondBranchOpcode(LastOpc)) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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if (isCondBranchOpcode(LastOpc)) {
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// Block ends with fall-through condbranch.
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parseCondBranch(LastInst, TBB, Cond);
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return false;
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = &*I;
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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// If AllowModify is true and the block ends with two or more unconditional
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// branches, delete all but the first unconditional branch.
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if (AllowModify && isUncondBranchOpcode(LastOpc)) {
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while (isUncondBranchOpcode(SecondLastOpc)) {
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LastInst->eraseFromParent();
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LastInst = SecondLastInst;
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LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
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// Return now the only terminator is an unconditional branch.
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else {
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SecondLastInst = &*I;
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SecondLastOpc = SecondLastInst->getOpcode();
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}
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}
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}
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
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return true;
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// If the block ends with a B and a Bcc, handle it.
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if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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parseCondBranch(SecondLastInst, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed.
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if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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return false;
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}
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// ...likewise if it ends with an indirect branch followed by an unconditional
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// branch.
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if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return true;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded) const {
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assert(TBB && "insertBranch must not be told to insert a fallthrough");
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assert((Cond.size() <= 3) &&
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"Sparc branch conditions should have at most three components!");
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if (Cond.empty()) {
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded = 8;
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return 1;
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}
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// Conditional branch
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unsigned Opc = Cond[0].getImm();
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unsigned CC = Cond[1].getImm();
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if (isRegCondBranchOpcode(Opc)) {
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Register Reg = Cond[2].getReg();
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BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC).addReg(Reg);
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} else {
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BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC);
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}
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if (!FBB) {
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if (BytesAdded)
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*BytesAdded = 8;
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return 1;
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}
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
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if (BytesAdded)
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*BytesAdded = 16;
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return 2;
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}
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unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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int Removed = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugInstr())
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continue;
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if (!isCondBranchOpcode(I->getOpcode()) &&
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!isUncondBranchOpcode(I->getOpcode()))
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break; // Not a branch
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Removed += getInstSizeInBytes(*I);
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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if (BytesRemoved)
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*BytesRemoved = Removed;
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return Count;
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}
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bool SparcInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() <= 3);
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SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm());
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Cond[1].setImm(GetOppositeBranchCondition(CC));
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return false;
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}
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bool SparcInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
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int64_t Offset) const {
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assert((Offset & 0b11) == 0 && "Malformed branch offset");
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switch (BranchOpc) {
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case SP::BA:
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case SP::BCOND:
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case SP::BCONDA:
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case SP::FBCOND:
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case SP::FBCONDA:
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return isIntN(22, Offset >> 2);
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case SP::BPICC:
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case SP::BPICCA:
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case SP::BPICCNT:
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case SP::BPICCANT:
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case SP::BPXCC:
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case SP::BPXCCA:
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case SP::BPXCCNT:
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case SP::BPXCCANT:
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case SP::BPFCC:
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case SP::BPFCCA:
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case SP::BPFCCNT:
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case SP::BPFCCANT:
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case SP::FBCOND_V9:
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case SP::FBCONDA_V9:
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return isIntN(BPccDisplacementBits, Offset >> 2);
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case SP::BPR:
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case SP::BPRA:
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case SP::BPRNT:
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case SP::BPRANT:
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return isIntN(BPrDisplacementBits, Offset >> 2);
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}
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llvm_unreachable("Unknown branch instruction!");
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}
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void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, Register DestReg,
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Register SrcReg, bool KillSrc,
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bool RenamableDest, bool RenamableSrc) const {
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unsigned numSubRegs = 0;
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unsigned movOpc = 0;
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const unsigned *subRegIdx = nullptr;
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bool ExtraG0 = false;
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const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
|
|
const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
|
|
const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
|
|
const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
|
|
SP::sub_odd64_then_sub_even,
|
|
SP::sub_odd64_then_sub_odd };
|
|
|
|
if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
|
|
BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
|
|
subRegIdx = DW_SubRegsIdx;
|
|
numSubRegs = 2;
|
|
movOpc = SP::ORrr;
|
|
ExtraG0 = true;
|
|
} else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
|
|
BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
|
|
if (Subtarget.isV9()) {
|
|
BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
} else {
|
|
// Use two FMOVS instructions.
|
|
subRegIdx = DFP_FP_SubRegsIdx;
|
|
numSubRegs = 2;
|
|
movOpc = SP::FMOVS;
|
|
}
|
|
} else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
|
|
if (Subtarget.isV9()) {
|
|
if (Subtarget.hasHardQuad()) {
|
|
BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
} else {
|
|
// Use two FMOVD instructions.
|
|
subRegIdx = QFP_DFP_SubRegsIdx;
|
|
numSubRegs = 2;
|
|
movOpc = SP::FMOVD;
|
|
}
|
|
} else {
|
|
// Use four FMOVS instructions.
|
|
subRegIdx = QFP_FP_SubRegsIdx;
|
|
numSubRegs = 4;
|
|
movOpc = SP::FMOVS;
|
|
}
|
|
} else if (SP::ASRRegsRegClass.contains(DestReg) &&
|
|
SP::IntRegsRegClass.contains(SrcReg)) {
|
|
BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
|
|
.addReg(SP::G0)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
} else if (SP::IntRegsRegClass.contains(DestReg) &&
|
|
SP::ASRRegsRegClass.contains(SrcReg)) {
|
|
BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
} else
|
|
llvm_unreachable("Impossible reg-to-reg copy");
|
|
|
|
if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
|
|
return;
|
|
|
|
const TargetRegisterInfo *TRI = &getRegisterInfo();
|
|
MachineInstr *MovMI = nullptr;
|
|
|
|
for (unsigned i = 0; i != numSubRegs; ++i) {
|
|
Register Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
|
|
Register Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
|
|
assert(Dst && Src && "Bad sub-register");
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
|
|
if (ExtraG0)
|
|
MIB.addReg(SP::G0);
|
|
MIB.addReg(Src);
|
|
MovMI = MIB.getInstr();
|
|
}
|
|
// Add implicit super-register defs and kills to the last MovMI.
|
|
MovMI->addRegisterDefined(DestReg, TRI);
|
|
if (KillSrc)
|
|
MovMI->addRegisterKilled(SrcReg, TRI);
|
|
}
|
|
|
|
void SparcInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
Register SrcReg, bool isKill, int FI,
|
|
const TargetRegisterClass *RC,
|
|
Register VReg,
|
|
MachineInstr::MIFlag Flags) const {
|
|
DebugLoc DL;
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
const MachineFrameInfo &MFI = MF->getFrameInfo();
|
|
MachineMemOperand *MMO = MF->getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
|
|
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
|
|
|
|
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
|
|
if (RC == &SP::I64RegsRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
|
|
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
|
|
else if (RC == &SP::IntRegsRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
|
|
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
|
|
else if (RC == &SP::IntPairRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
|
|
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
|
|
else if (RC == &SP::FPRegsRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
|
|
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
|
|
else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
|
|
BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
|
|
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
|
|
else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
|
|
// Use STQFri irrespective of its legality. If STQ is not legal, it will be
|
|
// lowered into two STDs in eliminateFrameIndex.
|
|
BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
|
|
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
|
|
else
|
|
llvm_unreachable("Can't store this register to stack slot");
|
|
}
|
|
|
|
void SparcInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
Register DestReg, int FI,
|
|
const TargetRegisterClass *RC,
|
|
Register VReg, unsigned SubReg,
|
|
MachineInstr::MIFlag Flags) const {
|
|
DebugLoc DL;
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
const MachineFrameInfo &MFI = MF->getFrameInfo();
|
|
MachineMemOperand *MMO = MF->getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
|
|
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
|
|
|
|
if (RC == &SP::I64RegsRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
|
|
.addMemOperand(MMO);
|
|
else if (RC == &SP::IntRegsRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
|
|
.addMemOperand(MMO);
|
|
else if (RC == &SP::IntPairRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
|
|
.addMemOperand(MMO);
|
|
else if (RC == &SP::FPRegsRegClass)
|
|
BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
|
|
.addMemOperand(MMO);
|
|
else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
|
|
BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
|
|
.addMemOperand(MMO);
|
|
else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
|
|
// Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
|
|
// lowered into two LDDs in eliminateFrameIndex.
|
|
BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
|
|
.addMemOperand(MMO);
|
|
else
|
|
llvm_unreachable("Can't load this register from stack slot");
|
|
}
|
|
|
|
Register SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
|
|
SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
|
|
Register GlobalBaseReg = SparcFI->getGlobalBaseReg();
|
|
if (GlobalBaseReg)
|
|
return GlobalBaseReg;
|
|
|
|
// Insert the set of GlobalBaseReg into the first MBB of the function
|
|
MachineBasicBlock &FirstMBB = MF->front();
|
|
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
|
|
const TargetRegisterClass *PtrRC =
|
|
Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
|
|
GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
|
|
|
|
DebugLoc dl;
|
|
|
|
BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
|
|
SparcFI->setGlobalBaseReg(GlobalBaseReg);
|
|
return GlobalBaseReg;
|
|
}
|
|
|
|
unsigned SparcInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
|
unsigned Opcode = MI.getOpcode();
|
|
|
|
if (MI.isInlineAsm()) {
|
|
const MachineFunction *MF = MI.getParent()->getParent();
|
|
const char *AsmStr = MI.getOperand(0).getSymbolName();
|
|
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
|
|
}
|
|
|
|
if (MI.getOpcode() == SP::GETPCX) {
|
|
const TargetMachine &TM = MI.getParent()->getParent()->getTarget();
|
|
if (TM.isPositionIndependent())
|
|
return 16;
|
|
switch (TM.getCodeModel()) {
|
|
default:
|
|
llvm_unreachable("Unsupported absolute code model");
|
|
case CodeModel::Small:
|
|
return 8;
|
|
case CodeModel::Medium:
|
|
return 16;
|
|
case CodeModel::Large:
|
|
return 24;
|
|
}
|
|
}
|
|
|
|
// If the instruction has a delay slot, be conservative and also include
|
|
// it for sizing purposes. This is done so that the BranchRelaxation pass
|
|
// will not mistakenly mark out-of-range branches as in-range.
|
|
if (MI.hasDelaySlot())
|
|
return get(Opcode).getSize() * 2;
|
|
return get(Opcode).getSize();
|
|
}
|
|
|
|
bool SparcInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
|
|
Register &SrcReg2, int64_t &CmpMask,
|
|
int64_t &CmpValue) const {
|
|
Register DstReg;
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
break;
|
|
case SP::SUBCCri:
|
|
DstReg = MI.getOperand(0).getReg();
|
|
SrcReg = MI.getOperand(1).getReg();
|
|
SrcReg2 = 0;
|
|
CmpMask = ~0;
|
|
CmpValue = MI.getOperand(2).getImm();
|
|
return DstReg == SP::G0 && CmpValue == 0;
|
|
case SP::SUBCCrr:
|
|
DstReg = MI.getOperand(0).getReg();
|
|
SrcReg = MI.getOperand(1).getReg();
|
|
SrcReg2 = MI.getOperand(2).getReg();
|
|
CmpMask = ~0;
|
|
CmpValue = 0;
|
|
return DstReg == SP::G0 && SrcReg2 == SP::G0;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool SparcInstrInfo::optimizeCompareInstr(
|
|
MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
|
|
int64_t CmpValue, const MachineRegisterInfo *MRI) const {
|
|
|
|
// Get the unique definition of SrcReg.
|
|
MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
|
|
if (!MI)
|
|
return false;
|
|
|
|
// Only optimize if defining and comparing instruction in same block.
|
|
if (MI->getParent() != CmpInstr.getParent())
|
|
return false;
|
|
|
|
unsigned NewOpcode;
|
|
switch (MI->getOpcode()) {
|
|
case SP::ANDNrr:
|
|
NewOpcode = SP::ANDNCCrr;
|
|
break;
|
|
case SP::ANDNri:
|
|
NewOpcode = SP::ANDNCCri;
|
|
break;
|
|
case SP::ANDrr:
|
|
NewOpcode = SP::ANDCCrr;
|
|
break;
|
|
case SP::ANDri:
|
|
NewOpcode = SP::ANDCCri;
|
|
break;
|
|
case SP::ORrr:
|
|
NewOpcode = SP::ORCCrr;
|
|
break;
|
|
case SP::ORri:
|
|
NewOpcode = SP::ORCCri;
|
|
break;
|
|
case SP::ORNCCrr:
|
|
NewOpcode = SP::ORNCCrr;
|
|
break;
|
|
case SP::ORNri:
|
|
NewOpcode = SP::ORNCCri;
|
|
break;
|
|
case SP::XORrr:
|
|
NewOpcode = SP::XORCCrr;
|
|
break;
|
|
case SP::XNORri:
|
|
NewOpcode = SP::XNORCCri;
|
|
break;
|
|
case SP::XNORrr:
|
|
NewOpcode = SP::XNORCCrr;
|
|
break;
|
|
case SP::ADDrr:
|
|
NewOpcode = SP::ADDCCrr;
|
|
break;
|
|
case SP::ADDri:
|
|
NewOpcode = SP::ADDCCri;
|
|
break;
|
|
case SP::SUBrr:
|
|
NewOpcode = SP::SUBCCrr;
|
|
break;
|
|
case SP::SUBri:
|
|
NewOpcode = SP::SUBCCri;
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
bool IsICCModified = false;
|
|
MachineBasicBlock::iterator I = MI;
|
|
MachineBasicBlock::iterator C = CmpInstr;
|
|
MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
|
|
const TargetRegisterInfo *TRI = &getRegisterInfo();
|
|
|
|
// If ICC is used or modified between MI and CmpInstr we cannot optimize.
|
|
while (++I != C) {
|
|
if (I->modifiesRegister(SP::ICC, TRI) || I->readsRegister(SP::ICC, TRI))
|
|
return false;
|
|
}
|
|
|
|
while (++I != E) {
|
|
// Only allow conditionals on equality.
|
|
if (I->readsRegister(SP::ICC, TRI)) {
|
|
bool IsICCBranch = I->getOpcode() == SP::BCOND ||
|
|
I->getOpcode() == SP::BPICC ||
|
|
I->getOpcode() == SP::BPXCC;
|
|
bool IsICCMove =
|
|
I->getOpcode() == SP::MOVICCrr || I->getOpcode() == SP::MOVICCri ||
|
|
I->getOpcode() == SP::MOVXCCrr || I->getOpcode() == SP::MOVXCCri;
|
|
bool IsICCConditional = IsICCBranch || IsICCMove;
|
|
if (!IsICCConditional ||
|
|
(I->getOperand(IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_E &&
|
|
I->getOperand(IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_NE))
|
|
return false;
|
|
} else if (I->modifiesRegister(SP::ICC, TRI)) {
|
|
IsICCModified = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!IsICCModified) {
|
|
MachineBasicBlock *MBB = CmpInstr.getParent();
|
|
if (any_of(MBB->successors(),
|
|
[](MachineBasicBlock *Succ) { return Succ->isLiveIn(SP::ICC); }))
|
|
return false;
|
|
}
|
|
|
|
if (MRI->hasOneNonDBGUse(SrcReg))
|
|
MI->getOperand(0).setReg(SP::G0);
|
|
|
|
MI->setDesc(get(NewOpcode));
|
|
MI->addRegisterDefined(SP::ICC);
|
|
CmpInstr.eraseFromParent();
|
|
|
|
return true;
|
|
}
|
|
|
|
bool SparcInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
|
|
switch (MI.getOpcode()) {
|
|
case TargetOpcode::LOAD_STACK_GUARD: {
|
|
assert(Subtarget.getTargetTriple().isOSLinux() &&
|
|
"Only Linux target is expected to contain LOAD_STACK_GUARD");
|
|
// offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc.
|
|
const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
|
|
MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
|
|
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
|
|
.addReg(SP::G7)
|
|
.addImm(Offset);
|
|
return true;
|
|
}
|
|
case SP::V8BAR: {
|
|
assert(!Subtarget.isV9() &&
|
|
"V8BAR should not be emitted on V9 processors!");
|
|
|
|
// Emit stbar; ldstub [%sp-1], %g0
|
|
// The sequence acts as a full barrier on V8 systems.
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineInstr &InstSTBAR =
|
|
*BuildMI(MBB, MI, MI.getDebugLoc(), get(SP::STBAR));
|
|
MachineInstr &InstLDSTUB =
|
|
*BuildMI(MBB, MI, MI.getDebugLoc(), get(SP::LDSTUBri), SP::G0)
|
|
.addReg(SP::O6)
|
|
.addImm(-1);
|
|
MIBundleBuilder(MBB, InstSTBAR, InstLDSTUB);
|
|
MBB.erase(MI);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|