23af867e6d
Correctly inform transform passes about our registers; this prevents the issue with the `find-last` test where the loop vectorizer pass mistakenly thinks that the backend has vector capabilities and generates vector types, which causes the backend to crash. See also: https://github.com/sparclinux/issues/issues/69
72 lines
2.2 KiB
C++
72 lines
2.2 KiB
C++
//===-- SparcTargetTransformInfo.cpp - SPARC specific TTI -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "SparcTargetTransformInfo.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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#define DEBUG_TYPE "sparctti"
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TargetTransformInfo::PopcntSupportKind
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SparcTTIImpl::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Type width must be power of 2");
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if (ST->usePopc())
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return TTI::PSK_FastHardware;
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return TTI::PSK_Software;
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}
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unsigned SparcTTIImpl::getRegisterClassForType(bool Vector, Type *Ty) const {
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if (Vector)
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return VRRC;
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if (Ty &&
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(Ty->getScalarType()->isFloatTy() || Ty->getScalarType()->isDoubleTy()))
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return FPRRC;
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if (Ty && (Ty->getScalarType()->isFP128Ty()))
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return FP128RRC;
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return GPRRC;
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}
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unsigned SparcTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
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switch (ClassID) {
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case GPRRC:
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// %g0, %g6, %g7, %o6, %i6, and %i7 are used for special purposes so we
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// discount them here.
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return 26;
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case FPRRC:
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return 32;
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case FP128RRC:
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return 16;
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case VRRC:
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// TODO We have vector capabilities as part of the VIS extensions, but the
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// codegen doesn't currently use it. Revisit this when vector codegen is
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// ready.
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return 0;
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}
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llvm_unreachable("Unsupported register class");
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}
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TypeSize
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SparcTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
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switch (K) {
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case TargetTransformInfo::RGK_Scalar:
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// TODO When targeting V8+ ABI, G and O registers are 64-bit.
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return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
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case TargetTransformInfo::RGK_FixedWidthVector:
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// TODO We have vector capabilities as part of the VIS extensions, but the
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// codegen doesn't currently use it. Revisit this when vector codegen is
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// ready.
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return TypeSize::getFixed(0);
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case TargetTransformInfo::RGK_ScalableVector:
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return TypeSize::getScalable(0);
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}
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llvm_unreachable("Unsupported register kind");
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}
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