aad7259ff6
This change improves memset code generation for non-zero values on AArch64 by using NEON's DUP instruction instead of the less efficient multiplication with 0x01010101 pattern. For small sizes, the value is extracted from a larger DUP. For non-power-of-two sizes, overlapping stores are used in some cases. TargetLowering::findOptimalMemOpLowering is modified to allow explicitly specifying the size of the constant in cases where the constant is larger than the store operations. Fixes #165949
519 lines
25 KiB
C++
519 lines
25 KiB
C++
//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that SystemZ uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include <optional>
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namespace llvm {
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namespace SystemZICMP {
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// Describes whether an integer comparison needs to be signed or unsigned,
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// or whether either type is OK.
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enum {
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Any,
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UnsignedOnly,
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SignedOnly
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};
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} // end namespace SystemZICMP
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class SystemZSubtarget;
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class SystemZTargetLowering : public TargetLowering {
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public:
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explicit SystemZTargetLowering(const TargetMachine &TM,
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const SystemZSubtarget &STI);
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bool useSoftFloat() const override;
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// Override TargetLowering.
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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return MVT::i32;
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}
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unsigned getVectorIdxWidth(const DataLayout &DL) const override {
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// Only the lower 12 bits of an element index are used, so we don't
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// want to clobber the upper 32 bits of a GPR unnecessarily.
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return 32;
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}
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TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
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const override {
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// Widen subvectors to the full width rather than promoting integer
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// elements. This is better because:
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//
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// (a) it means that we can handle the ABI for passing and returning
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// sub-128 vectors without having to handle them as legal types.
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//
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// (b) we don't have instructions to extend on load and truncate on store,
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// so promoting the integers is less efficient.
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//
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// (c) there are no multiplication instructions for the widest integer
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// type (v2i64).
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// Expand (narrow) f16 vectors during type legalization to avoid
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// operations for all elements as with expansion after widening.
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if (VT.getScalarType() == MVT::f16)
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return VT.getVectorElementCount().isScalar() ? TypeScalarizeVector
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: TypeSplitVector;
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if (VT.getScalarSizeInBits() % 8 == 0)
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return TypeWidenVector;
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return TargetLoweringBase::getPreferredVectorAction(VT);
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}
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unsigned
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getNumRegisters(LLVMContext &Context, EVT VT,
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std::optional<MVT> RegisterVT) const override {
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// i128 inline assembly operand.
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if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
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return 1;
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return TargetLowering::getNumRegisters(Context, VT);
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}
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unsigned
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getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC,
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EVT VT, EVT &IntermediateVT,
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unsigned &NumIntermediates,
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MVT &RegisterVT) const override;
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MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
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EVT VT) const override;
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unsigned getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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bool isCheapToSpeculateCtlz(Type *) const override { return true; }
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bool isCheapToSpeculateCttz(Type *) const override { return true; }
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bool preferZeroCompareBranch() const override { return true; }
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bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
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ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
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return Mask && Mask->getValue().isIntN(16);
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}
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bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
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return VT.isScalarInteger();
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}
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
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EVT) const override;
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT VT) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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bool ShouldShrinkFPConstant(EVT VT) const override {
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// Do not shrink 64-bit FP constpool entries since LDEB is slower than
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// LD, and having the full constant in memory enables reg/mem opcodes.
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return VT != MVT::f64;
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}
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MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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bool hasInlineStackProbe(const MachineFunction &MF) const override;
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AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override;
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AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override;
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AtomicExpansionKind
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shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const override;
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bool isLegalICmpImmediate(int64_t Imm) const override;
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bool isLegalAddImmediate(int64_t Imm) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
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MachineMemOperand::Flags Flags,
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unsigned *Fast) const override;
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bool findOptimalMemOpLowering(LLVMContext &Context, std::vector<EVT> &MemOps,
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unsigned Limit, const MemOp &Op, unsigned DstAS,
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unsigned SrcAS,
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const AttributeList &FuncAttributes,
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EVT *LargestVT = nullptr) const override;
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EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
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const AttributeList &FuncAttributes) const override;
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bool isTruncateFree(Type *, Type *) const override;
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bool isTruncateFree(EVT, EVT) const override;
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bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
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bool MathUsed) const override {
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// Form add and sub with overflow intrinsics regardless of any extra
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// users of the math result.
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return VT == MVT::i32 || VT == MVT::i64 || VT == MVT::i128;
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}
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bool shouldConsiderGEPOffsetSplit() const override { return true; }
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bool preferSelectsOverBooleanArithmetic(EVT VT) const override {
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return true;
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}
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// This function currently returns cost for srl/ipm/cc sequence for merging.
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CondMergingParams
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getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
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const Value *Rhs) const override;
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// Handle Lowering flag assembly outputs.
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SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
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const SDLoc &DL,
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const AsmOperandInfo &Constraint,
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SelectionDAG &DAG) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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TargetLowering::ConstraintType
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getConstraintType(StringRef Constraint) const override;
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TargetLowering::ConstraintWeight
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getSingleConstraintMatchWeight(AsmOperandInfo &info,
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const char *constraint) const override;
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void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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InlineAsm::ConstraintCode
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode.size() == 1) {
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switch(ConstraintCode[0]) {
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default:
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break;
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case 'o':
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return InlineAsm::ConstraintCode::o;
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case 'Q':
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return InlineAsm::ConstraintCode::Q;
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case 'R':
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return InlineAsm::ConstraintCode::R;
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case 'S':
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return InlineAsm::ConstraintCode::S;
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case 'T':
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return InlineAsm::ConstraintCode::T;
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}
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} else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {
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switch (ConstraintCode[1]) {
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default:
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break;
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case 'Q':
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return InlineAsm::ConstraintCode::ZQ;
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case 'R':
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return InlineAsm::ConstraintCode::ZR;
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case 'S':
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return InlineAsm::ConstraintCode::ZS;
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case 'T':
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return InlineAsm::ConstraintCode::ZT;
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}
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}
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return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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}
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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Register
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getExceptionPointerRegister(const Constant *PersonalityFn) const override;
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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Register
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
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/// Override to support customized stack guard loading.
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bool useLoadStackGuardNode(const Module &M) const override { return true; }
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void
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insertSSPDeclarations(Module &M,
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const LibcallLoweringInfo &Libcalls) const override {}
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const override;
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const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
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bool allowTruncateForTailCall(Type *, Type *) const override;
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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bool splitValueIntoRegisterParts(
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SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
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unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
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const override;
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SDValue joinRegisterPartsIntoValue(
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SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
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unsigned NumParts, MVT PartVT, EVT ValueVT,
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std::optional<CallingConv::ID> CC) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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std::pair<SDValue, SDValue>
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makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName,
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EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv,
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bool IsSigned, SDLoc DL, bool DoesNotReturn,
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bool IsReturnValueUsed) const;
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SDValue useLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, MVT VT, SDValue Arg,
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SDLoc DL, SDValue Chain, bool IsStrict) const;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context,
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const Type *RetTy) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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/// Determine which of the bits specified in Mask are known to be either
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/// zero or one and return them in the KnownZero/KnownOne bitsets.
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void computeKnownBitsForTargetNode(const SDValue Op,
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KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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/// Determine the number of bits in the operation that are sign bits.
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(
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SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
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bool PoisonOnly, unsigned Depth) const override;
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ISD::NodeType getExtendForAtomicOps() const override {
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return ISD::ANY_EXTEND;
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}
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ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
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return ISD::ZERO_EXTEND;
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}
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bool supportSwiftError() const override {
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return true;
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}
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unsigned getStackProbeSize(const MachineFunction &MF) const;
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bool hasAndNot(SDValue Y) const override;
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private:
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const SystemZSubtarget &Subtarget;
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// Implement LowerOperation for individual opcodes.
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SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
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const SDLoc &DL, EVT VT,
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SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
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SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
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EVT VT, ISD::CondCode CC,
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SDValue CmpOp0, SDValue CmpOp1,
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SDValue Chain = SDValue(),
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bool IsSignaling = false) const;
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SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
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bool IsSignaling) const;
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SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
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SelectionDAG &DAG, unsigned Opcode,
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SDValue GOTOffset) const;
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SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(BlockAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART_ELF(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART_XPLINK(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerMULH(SDValue Op, SelectionDAG &DAG, unsigned Opcode) const;
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SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVECREDUCE_ADD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_LDST_I128(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
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unsigned Opcode) const;
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SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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bool isVectorElementLoad(SDValue Op) const;
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SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
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SmallVectorImpl<SDValue> &Elems) const;
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
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SDValue lowerFSHL(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFSHR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue lower_FP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lower_INT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerLoadF16(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerStoreF16(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
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bool canTreatAsByteVector(EVT VT) const;
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SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
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unsigned Index, DAGCombinerInfo &DCI,
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bool Force) const;
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SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
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DAGCombinerInfo &DCI) const;
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SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
bool canLoadStoreByteSwapped(EVT VT) const;
|
|
SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineFCOPYSIGN(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineSETCC(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineShiftToMulAddHigh(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
|
|
SDValue unwrapAddress(SDValue N) const override;
|
|
|
|
// If the last instruction before MBBI in MBB was some form of COMPARE,
|
|
// try to replace it with a COMPARE AND BRANCH just before MBBI.
|
|
// CCMask and Target are the BRC-like operands for the branch.
|
|
// Return true if the change was made.
|
|
bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned CCMask,
|
|
MachineBasicBlock *Target) const;
|
|
|
|
// Implement EmitInstrWithCustomInserter for individual operation types.
|
|
MachineBasicBlock *emitAdjCallStack(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
|
|
MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
|
|
unsigned StoreOpcode, unsigned STOCOpcode,
|
|
bool Invert) const;
|
|
MachineBasicBlock *emitICmp128Hi(MachineInstr &MI, MachineBasicBlock *BB,
|
|
bool Unsigned) const;
|
|
MachineBasicBlock *emitPair128(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
|
|
bool ClearEven) const;
|
|
MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
|
|
MachineBasicBlock *BB,
|
|
unsigned BinOpcode,
|
|
bool Invert = false) const;
|
|
MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned CompareOpcode,
|
|
unsigned KeepOldMask) const;
|
|
MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
|
|
unsigned Opcode,
|
|
bool IsMemset = false) const;
|
|
MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
|
|
unsigned Opcode) const;
|
|
MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned Opcode, bool NoFloat) const;
|
|
MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned Opcode) const;
|
|
MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
|
|
|
|
MachineMemOperand::Flags
|
|
getTargetMMOFlags(const Instruction &I) const override;
|
|
const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
|
|
|
|
private:
|
|
bool isInternal(const Function *Fn) const;
|
|
mutable std::map<const Function *, bool> IsInternalCache;
|
|
void verifyNarrowIntegerArgs_Call(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const Function *F, SDValue Callee) const;
|
|
void verifyNarrowIntegerArgs_Ret(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const Function *F) const;
|
|
bool
|
|
verifyNarrowIntegerArgs(const SmallVectorImpl<ISD::OutputArg> &Outs) const;
|
|
|
|
public:
|
|
};
|
|
|
|
struct SystemZVectorConstantInfo {
|
|
private:
|
|
APInt IntBits; // The 128 bits as an integer.
|
|
APInt SplatBits; // Smallest splat value.
|
|
APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
|
|
unsigned SplatBitSize = 0;
|
|
bool isFP128 = false;
|
|
public:
|
|
unsigned Opcode = 0;
|
|
SmallVector<unsigned, 2> OpVals;
|
|
MVT VecVT;
|
|
SystemZVectorConstantInfo(APInt IntImm);
|
|
SystemZVectorConstantInfo(APFloat FPImm)
|
|
: SystemZVectorConstantInfo(FPImm.bitcastToAPInt()) {
|
|
isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
|
|
}
|
|
SystemZVectorConstantInfo(BuildVectorSDNode *BVN);
|
|
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|