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llvm-project/llvm/test/MachineVerifier/AMDGPU
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Matt Arsenault 694a488708
AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (#154499)
64-bit version of 7425af4b7aaa31da10bd1bc7996d3bb212c79d88. We
still need to lower to 32-bit v_accagpr_write_b32s, so this has
a unique value restriction that requires both halves of the constant
to be 32-bit inline immediates. This only introduces the new
pseudo definitions, but doesn't try to use them yet.
2025-08-20 22:54:37 +09:00
..
av_mov_b64_imm_pseudo.mir
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fix-illegal-vector-copies.mir
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issue98474-missing-def-liveout-physical-subregister.mir
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lit.local.cfg
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register-killed-inside-loop.mir
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test_g_bitcast.mir
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test_g_incompatible_range.mir
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test_g_intrinsic_w_side_effects.mir
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test_g_intrinsic.mir
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undef-should-only-be-set-on-subreg-defs.mir
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undef-virt-reg-entry-block.mir
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undef-virt-reg-nonentry-block.mir
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unsupported-subreg-index-aligned-vgpr-check.mir
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verifier-ec-subreg-liveness.mir
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verifier-implicit-virtreg-invalid-physreg-liveness.mir
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verifier-pseudo-terminators.mir
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verifier-sdwa-selection.mir
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verify-av-mov-imm-pseudo.mir
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verify-implicit-def.mir
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verify-reg-sequence.mir
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writelane_m0.mir
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