ed5f8f238d
Add option `use-fn-table-in-decode-to-mcinst` to use a table of function pointers instead of a switch case in the generated `decodeToMCInst` function. When the number of switch cases in this function is large, the generated code takes a long time to compile in release builds. Using a table of function pointers instead improves the compile time significantly (~3x speedup in compiling the code in a downstream target). This option will allow targets to opt into this mode if they desire for better build times. Tested with `check-llvm-mc` with the option enabled by default.
85 lines
2.8 KiB
TableGen
85 lines
2.8 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -use-fn-table-in-decode-to-mcinst -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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let Namespace = "arch" in {
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def R0 : Register<"r0">;
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def R1 : Register<"r1">;
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def R2 : Register<"r2">;
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def R3 : Register<"r3">;
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}
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def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3)>;
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class TestInstruction : Instruction {
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let Size = 1;
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let OutOperandList = (outs);
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field bits<8> Inst;
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field bits<8> SoftFail = 0;
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}
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// Define instructions to generate 4 cases in decodeToMCInst.
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// Lower 2 bits define the number of operands. Each register operand
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// needs 2 bits to encode.
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// An instruction with no inputs. Encoded with lower 2 bits = 0 and upper
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// 6 bits = 0 as well.
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def Inst0 : TestInstruction {
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let Inst = 0x0;
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let InOperandList = (ins);
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let AsmString = "Inst0";
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}
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// An instruction with a single input. Encoded with lower 2 bits = 1 and the
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// single input in bits 2-3.
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def Inst1 : TestInstruction {
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bits<2> r0;
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let Inst{1-0} = 1;
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let Inst{3-2} = r0;
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let InOperandList = (ins Regs:$r0);
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let AsmString = "Inst1";
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}
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// An instruction with two inputs. Encoded with lower 2 bits = 2 and the
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// inputs in bits 2-3 and 4-5.
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def Inst2 : TestInstruction {
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bits<2> r0;
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bits<2> r1;
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let Inst{1-0} = 2;
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let Inst{3-2} = r0;
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let Inst{5-4} = r1;
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let InOperandList = (ins Regs:$r0, Regs:$r1);
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let AsmString = "Inst2";
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}
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// An instruction with three inputs. Encoded with lower 2 bits = 3 and the
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// inputs in bits 2-3 and 4-5 and 6-7.
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def Inst3 : TestInstruction {
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bits<2> r0;
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bits<2> r1;
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bits<2> r2;
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let Inst{1-0} = 3;
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let Inst{3-2} = r0;
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let Inst{5-4} = r1;
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let Inst{7-6} = r2;
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let InOperandList = (ins Regs:$r0, Regs:$r1, Regs:$r2);
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let AsmString = "Inst3";
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}
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// CHECK-LABEL: DecodeStatus decodeFn0(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: DecodeStatus decodeFn1(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: DecodeStatus decodeFn2(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: DecodeStatus decodeFn3(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK-LABEL: decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete)
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// CHECK: static constexpr DecodeFnTy decodeFnTable[]
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// CHECK-NEXT: decodeFn0,
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// CHECK-NEXT: decodeFn1,
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// CHECK-NEXT: decodeFn2,
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// CHECK-NEXT: decodeFn3,
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// CHECK: return decodeFnTable[Idx](S, insn, MI, Address, Decoder, DecodeComplete)
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