3459bb4f27
This is useful for `InstAlias` where a fixed register may depend on the
HwMode. The motivating use case for this is the RISC-V RVY ISA where
certain instructions mnemonics are remapped to take a different
register class depending on the HwMode and can be used as follows:
```
def NullReg : RegisterByHwMode<PtrRC, [RV32I, RV64I, RV64Y, RV64Y],
[X0, X0, X0_Y, X0_Y]>;
```
Pull Request: https://github.com/llvm/llvm-project/pull/175227
351 lines
17 KiB
TableGen
351 lines
17 KiB
TableGen
// RUN: llvm-tblgen --gen-compress-inst-emitter -I %p/../../include -I %S %s -o - | FileCheck %s
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include "Common/RegClassByHwModeCommon.td"
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def IsPtr64 : Predicate<"Subtarget->isPtr64()">;
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defvar Ptr32 = DefaultMode;
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def Ptr64 : HwMode<[IsPtr64]>;
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def PtrRC : RegClassByHwMode<[Ptr32, Ptr64], [XRegs, YRegs]>;
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def NullReg : RegisterByHwMode<PtrRC, [Ptr32, Ptr64], [X0, Y0]>;
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def X_MOV : TestInstruction {
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let OutOperandList = (outs XRegs:$dst);
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let InOperandList = (ins XRegs:$src);
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let AsmString = "x_mov $dst, $src";
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let opcode = 0;
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}
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def X_MOV_SMALL : TestInstruction {
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let OutOperandList = (outs XRegs:$dst);
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let InOperandList = (ins XRegs:$src);
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let AsmString = "x_mov.small $dst, $src";
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let opcode = 1;
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let Size = 1;
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}
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def X_MOV_ZERO : TestInstruction {
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let OutOperandList = (outs XRegs:$dst);
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let InOperandList = (ins);
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let AsmString = "x_mov.zero $dst";
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let opcode = 2;
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let Size = 1;
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}
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def X_MOV_TIED : TestInstruction {
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let OutOperandList = (outs XRegs:$dst);
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let InOperandList = (ins XRegs:$src);
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let Constraints = "$src = $dst";
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let AsmString = "x_mov.tied $dst, $src";
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let opcode = 3;
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let Size = 1;
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}
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def PTR_MOV : TestInstruction {
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let OutOperandList = (outs PtrRC:$dst);
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let InOperandList = (ins PtrRC:$src);
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let AsmString = "ptr_mov $dst, $src";
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let opcode = 3;
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}
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def PTR_MOV_SMALL : TestInstruction {
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let OutOperandList = (outs PtrRC:$dst);
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let InOperandList = (ins PtrRC:$src);
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let AsmString = "ptr_mov.small $dst, $src";
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let opcode = 4;
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let Size = 1;
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}
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def PTR_MOV_ZERO : TestInstruction {
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let OutOperandList = (outs PtrRC:$dst);
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let InOperandList = (ins);
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let AsmString = "ptr_mov.zero $dst";
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let opcode = 3;
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let Size = 1;
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}
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def PTR_MOV_TIED : TestInstruction {
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let OutOperandList = (outs PtrRC:$dst);
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let InOperandList = (ins PtrRC:$src);
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let Constraints = "$src = $dst";
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let AsmString = "ptr_mov.tied $dst, $src";
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let opcode = 3;
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let Size = 1;
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}
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def : CompressPat<(X_MOV XRegs:$dst, X0),
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(X_MOV_ZERO XRegs:$dst)>;
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def : CompressPat<(X_MOV XRegs:$dst, XRegs:$dst),
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(X_MOV_TIED XRegs:$dst)>;
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def : CompressPat<(X_MOV XRegs:$dst, XRegs:$src),
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(X_MOV_SMALL XRegs:$dst, XRegs:$src)>;
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def : CompressPat<(PTR_MOV PtrRC:$dst, NullReg),
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(PTR_MOV_ZERO PtrRC:$dst)>;
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def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$dst),
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(PTR_MOV_TIED PtrRC:$dst)>;
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def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
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(PTR_MOV_SMALL PtrRC:$dst, PtrRC:$src)>;
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// CHECK: static bool compressInst(MCInst &OutInst,
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// CHECK-NEXT: const MCInst &MI,
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// CHECK-NEXT: const MCSubtargetInfo &STI) {
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// CHECK-NEXT: {{\[\[}}maybe_unused]] unsigned HwModeId = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
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// CHECK-NEXT: switch (MI.getOpcode()) {
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// CHECK-NEXT: default: return false;
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// CHECK-NEXT: case MyTarget::PTR_MOV: {
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// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
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// CHECK-NEXT: (MI.getOperand(1).getReg() == MyTarget::RegisterByHwMode::getNullReg(HwModeId)) &&
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// CHECK-NEXT: MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg())) {
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// CHECK-NEXT: // ptr_mov.zero $dst
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::PTR_MOV_ZERO);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
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// CHECK-NEXT: (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // ptr_mov.tied $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::PTR_MOV_TIED);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // ptr_mov.small $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::PTR_MOV_SMALL);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case PTR_MOV
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// CHECK-NEXT: case MyTarget::X_MOV: {
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// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
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// CHECK-NEXT: (MI.getOperand(1).getReg() == MyTarget::X0) &&
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// CHECK-NEXT: MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg())) {
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// CHECK-NEXT: // x_mov.zero $dst
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::X_MOV_ZERO);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
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// CHECK-NEXT: (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // x_mov.tied $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::X_MOV_TIED);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // x_mov.small $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::X_MOV_SMALL);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case X_MOV
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// CHECK-NEXT: } // switch
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// CHECK-NEXT: return false;
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// CHECK-NEXT: }
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// CHECK: static bool uncompressInst(MCInst &OutInst,
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// CHECK-NEXT: const MCInst &MI,
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// CHECK-NEXT: const MCSubtargetInfo &STI) {
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// CHECK-NEXT: {{\[\[}}maybe_unused]] unsigned HwModeId = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
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// CHECK-NEXT: switch (MI.getOpcode()) {
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// CHECK-NEXT: default: return false;
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// CHECK-NEXT: case MyTarget::PTR_MOV_SMALL: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // ptr_mov $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::PTR_MOV);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case PTR_MOV_SMALL
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// CHECK-NEXT: case MyTarget::PTR_MOV_TIED: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg())) {
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// CHECK-NEXT: // ptr_mov $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::PTR_MOV);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case PTR_MOV_TIED
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// CHECK-NEXT: case MyTarget::PTR_MOV_ZERO: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg())) {
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// CHECK-NEXT: // ptr_mov $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::PTR_MOV);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MCOperand::createReg(MyTarget::RegisterByHwMode::getNullReg(HwModeId)));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case PTR_MOV_ZERO
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// CHECK-NEXT: case MyTarget::X_MOV_SMALL: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // x_mov $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::X_MOV);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case X_MOV_SMALL
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// CHECK-NEXT: case MyTarget::X_MOV_TIED: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg())) {
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// CHECK-NEXT: // x_mov $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::X_MOV);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case X_MOV_TIED
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// CHECK-NEXT: case MyTarget::X_MOV_ZERO: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg())) {
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// CHECK-NEXT: // x_mov $dst, $src
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// CHECK-NEXT: OutInst.setOpcode(MyTarget::X_MOV);
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: OutInst.addOperand(MCOperand::createReg(MyTarget::X0));
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// CHECK-NEXT: OutInst.setLoc(MI.getLoc());
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case X_MOV_ZERO
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// CHECK-NEXT: } // switch
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// CHECK-NEXT: return false;
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// CHECK-NEXT: }
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// CHECK: static bool isCompressibleInst(const MachineInstr &MI,
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// CHECK-NEXT: const MyTargetSubtarget &STI) {
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// CHECK-NEXT: {{\[\[}}maybe_unused]] unsigned HwModeId = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
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// CHECK-NEXT: switch (MI.getOpcode()) {
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// CHECK-NEXT: default: return false;
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// CHECK-NEXT: case MyTarget::PTR_MOV: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // ptr_mov.small $dst, $src
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
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// CHECK-NEXT: (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // ptr_mov.tied $dst, $src
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
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// CHECK-NEXT: (MI.getOperand(1).getReg() == MyTarget::RegisterByHwMode::getNullReg(HwModeId)) &&
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// CHECK-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]].contains(MI.getOperand(0).getReg())) {
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// CHECK-NEXT: // ptr_mov.zero $dst
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: break;
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// CHECK-NEXT: } // case PTR_MOV
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// CHECK-NEXT: case MyTarget::X_MOV: {
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// CHECK-NEXT: if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // x_mov.small $dst, $src
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
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// CHECK-NEXT: (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
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// CHECK-NEXT: MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isPhysical() &&
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// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(1).getReg())) {
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// CHECK-NEXT: // x_mov.tied $dst, $src
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// CHECK-NEXT: // Operand: dst
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// CHECK-NEXT: // Operand: src
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// CHECK-NEXT: return true;
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// CHECK-NEXT: } // if
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// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
|
|
// CHECK-NEXT: (MI.getOperand(1).getReg() == MyTarget::X0) &&
|
|
// CHECK-NEXT: MI.getOperand(0).isReg() && MI.getOperand(0).getReg().isPhysical() &&
|
|
// CHECK-NEXT: MyTargetMCRegisterClasses[MyTarget::XRegsRegClassID].contains(MI.getOperand(0).getReg())) {
|
|
// CHECK-NEXT: // x_mov.zero $dst
|
|
// CHECK-NEXT: // Operand: dst
|
|
// CHECK-NEXT: return true;
|
|
// CHECK-NEXT: } // if
|
|
// CHECK-NEXT: break;
|
|
// CHECK-NEXT: } // case X_MOV
|
|
// CHECK-NEXT: } // switch
|
|
// CHECK-NEXT: return false;
|
|
// CHECK-NEXT: }
|
|
|
|
def MyTargetISA : InstrInfo;
|
|
def MyTargetAsmWriter : AsmWriter {
|
|
int PassSubtarget = 1;
|
|
}
|
|
def MyTarget : Target {
|
|
let InstructionSet = MyTargetISA;
|
|
let AssemblyWriters = [MyTargetAsmWriter];
|
|
}
|