3459bb4f27
This is useful for `InstAlias` where a fixed register may depend on the
HwMode. The motivating use case for this is the RISC-V RVY ISA where
certain instructions mnemonics are remapped to take a different
register class depending on the HwMode and can be used as follows:
```
def NullReg : RegisterByHwMode<PtrRC, [RV32I, RV64I, RV64Y, RV64Y],
[X0, X0, X0_Y, X0_Y]>;
```
Pull Request: https://github.com/llvm/llvm-project/pull/175227
142 lines
6.3 KiB
TableGen
142 lines
6.3 KiB
TableGen
// RUN: rm -rf %t && split-file %s %t
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// RUN: not llvm-tblgen --gen-asm-matcher -I %p/../../include -I %t -I %S \
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// RUN: %t/inst-alias-bad-reg.td -o /dev/null 2>&1 | FileCheck %t/inst-alias-bad-reg.td --implicit-check-not="error:"
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// RUN: not llvm-tblgen --gen-asm-matcher -I %p/../../include -I %t -I %S \
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// RUN: %t/inst-alias-static-predicates.td -o /dev/null 2>&1 | FileCheck %t/inst-alias-static-predicates.td --implicit-check-not="error:"
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// RUN: not llvm-tblgen --gen-compress-inst-emitter -I %p/../../include -I %t -I %S \
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// RUN: %t/compress-regclass-by-hwmode.td -o /dev/null 2>&1 | FileCheck %t/compress-regclass-by-hwmode.td --implicit-check-not="error:"
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// RUN: not llvm-tblgen --gen-compress-inst-emitter -I %p/../../include -I %t -I %S \
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// RUN: %t/compress-regclass-by-hwmode-2.td -o /dev/null 2>&1 | FileCheck %t/compress-regclass-by-hwmode-2.td --implicit-check-not="error:"
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// RUN: not llvm-tblgen --gen-dag-isel -I %p/../../include -I %t -I %S \
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// RUN: %t/vt-by-hwmode-missing.td -o /dev/null 2>&1 | FileCheck %t/vt-by-hwmode-missing.td --implicit-check-not="error:"
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// RUN: not llvm-tblgen --gen-dag-isel -I %p/../../include -I %t -I %S \
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// RUN: %t/multiple-entries-for-same-mode.td -o /dev/null 2>&1 | FileCheck %t/multiple-entries-for-same-mode.td --implicit-check-not="error:"
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//--- Common.td
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include "Common/RegClassByHwModeCommon.td"
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def IsPtr64 : Predicate<"Subtarget->isPtr64()">;
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def IsPtr32 : Predicate<"!Subtarget->isPtr64()">;
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defvar Ptr32 = DefaultMode;
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def Ptr64 : HwMode<[IsPtr64]>;
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def PtrRC : RegClassByHwMode<[Ptr32, Ptr64], [XRegs, YRegs]>;
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def PTR_MOV : TestInstruction {
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let OutOperandList = (outs PtrRC:$dst);
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let InOperandList = (ins PtrRC:$src);
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let AsmString = "ptr_mov $dst, $src";
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let opcode = 0;
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}
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//--- inst-alias-bad-reg.td
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include "Common.td"
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/// This should fail since X0 is not necessarily part of PtrRC.
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def BAD_REG : InstAlias<"ptr_zero $rd", (PTR_MOV PtrRC:$dst, X0)>;
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// CHECK: [[#@LINE-1]]:5: error: cannot resolve HwMode for PtrRC
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// CHECK: Common.td:7:5: note: PtrRC defined here
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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//--- inst-alias-static-predicates.td
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include "Common.td"
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/// In theory we could allow the following code since the predicates statically
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/// resolve to the correct register class, but since this is non-trivial, check
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// that we get a sensible-ish error instead.
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let Predicates = [IsPtr32] in
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def MOV_X0 : InstAlias<"mov_x0 $dst", (PTR_MOV PtrRC:$dst, X0)>;
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// CHECK: [[#@LINE-1]]:5: error: cannot resolve HwMode for PtrRC
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// CHECK: Common.td:7:5: note: PtrRC defined here
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let Predicates = [IsPtr64] in
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def MOV_Y0 : InstAlias<"mov_y0 $dst", (PTR_MOV PtrRC:$dst, Y0)>;
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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//--- compress-regclass-by-hwmode.td
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include "Common.td"
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def PTR_ZERO_SMALL : TestInstruction {
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let OutOperandList = (outs PtrRC:$dst);
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let InOperandList = (ins);
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let AsmString = "ptr_zero $dst";
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let opcode = 1;
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let Size = 1;
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}
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/// This should fail since X0 is not necessarily part of PtrRC.
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def : CompressPat<(PTR_MOV PtrRC:$dst, X0),
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(PTR_ZERO_SMALL PtrRC:$dst)>;
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// CHECK: [[#@LINE-2]]:1: error: Error in Dag '(PTR_MOV PtrRC:$dst, X0)': Register 'X0' is not in register class 'PtrRC'
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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//--- compress-regclass-by-hwmode-2.td
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include "Common.td"
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def X_MOV_BIG : TestInstruction {
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let OutOperandList = (outs XRegs:$dst);
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let InOperandList = (ins XRegs:$src);
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let AsmString = "x_mov $dst, $src";
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let opcode = 1;
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let Size = 4;
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}
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/// This should fail since PtrRC is not necessarily part of XRegs.
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/// In theory, this could be resolved depending on the Predicates but
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/// for not we should just always emit an error.
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let Predicates = [IsPtr32] in
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def : CompressPat<(X_MOV_BIG XRegs:$dst, XRegs:$src),
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(PTR_MOV PtrRC:$dst, PtrRC:$src)>;
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// CHECK: [[#@LINE-2]]:1: error: Type mismatch between Input and Output Dag operand 'dst'
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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//--- vt-by-hwmode-missing.td
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include "Common.td"
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/// This should fail since we are missing a DefaultMode entry for the
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/// ValueTypeByHwMode and can't resolve it for the Ptr32 (default) case.
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def BadVT : ValueTypeByHwMode<[Ptr64], [i64]>;
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def BadVTRegClass : RegisterClass<"MyTarget", [i64, BadVT], 64, (add Y0, Y1)>;
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/// NOTE: this error only occurs for RegClassByHwMode, normal RegisterClass
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/// logic for VT resolution takes a different code path and does not error.
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def TEST_OK : TestInstruction {
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let OutOperandList = (outs BadVTRegClass:$dst);
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let InOperandList = (ins BadVTRegClass:$src1, BadVTRegClass:$src2);
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let AsmString = "test $dst, $src1, $src2";
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let Pattern = [(set BadVTRegClass:$dst, (add BadVTRegClass:$src1, BadVTRegClass:$src2))];
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}
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/// Once we use RegClassByHwMode, we get an error about missing modes:
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def BadPtrRC : RegClassByHwMode<[Ptr32, Ptr64], [BadVTRegClass, YRegs]>;
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// CHECK: vt-by-hwmode-missing.td:[[#@LINE-1]]:5: error: Could not resolve VT for Mode DefaultMode
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// CHECK: vt-by-hwmode-missing.td:4:5: note: ValueTypeByHwMode BadVT defined here
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// CHECK: vt-by-hwmode-missing.td:[[#@LINE+1]]:5: note: pattern instantiated here
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def TEST : TestInstruction {
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let OutOperandList = (outs BadPtrRC:$dst);
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let InOperandList = (ins BadPtrRC:$src1, BadPtrRC:$src2);
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let AsmString = "test $dst, $src1, $src2";
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let opcode = 0;
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let Pattern = [(set BadPtrRC:$dst, (add BadPtrRC:$src1, BadPtrRC:$src2))];
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}
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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//--- multiple-entries-for-same-mode.td
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include "Common.td"
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/// We should get an error if the same mode is listed more than once
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defvar Ptr64Alias = Ptr64;
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def BadRegClass : RegClassByHwMode<[Ptr32, Ptr64, Ptr64Alias], [XRegs, YRegs, YRegs]>;
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// CHECK: [[#@LINE-1]]:5: error: duplicate RegisterClass entry for HwMode Ptr64: YRegs
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// Need at least one CompressPat use of the bad reg class to trigger the error:
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def USE_BAD_REG_CLASS : TestInstruction {
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let OutOperandList = (outs BadRegClass:$dst);
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let InOperandList = (ins BadRegClass:$src1, BadRegClass:$src2);
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let AsmString = "bad $dst";
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let Pattern = [(set BadRegClass:$dst, (add BadRegClass:$src1, BadRegClass:$src2))];
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}
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def MyTargetISA : InstrInfo;
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def MyTarget : Target {
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let InstructionSet = MyTargetISA;
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}
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