40ddde5d1f
Tablegen currently expects targets to have at least one pressure set for every broader register category. AMDGPU's VGPR or AGPR, for instance, seemed to work correctly without any pset, though we have forced one for each type to avoid the assertion in computeRegUnitSets. However, psets can not be entirely empty. At least one set is mandatory for every target. This patch bypasses the assertion for the classes when GeneratePressureSet is zero while ensuring the RegUnitSets are not empty. Reviewed By: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D110305
16 lines
373 B
TableGen
16 lines
373 B
TableGen
// RUN: not llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s 2>&1 | FileCheck %s
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// Negative test to check empty Psets for a target.
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include "llvm/Target/Target.td"
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def R : Register<"r">;
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def R_32 : RegisterClass<"MyTarget", [i32], 32, (add R)> {
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let GeneratePressureSet = 0;
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}
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def MyTarget : Target;
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// CHECK: error: RegUnitSets cannot be empty!
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