36 lines
1.0 KiB
TableGen
36 lines
1.0 KiB
TableGen
// RUN: not llvm-tblgen -gen-register-info -I %p/../../include %s 2>&1 | FileCheck %s
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include "llvm/Target/Target.td"
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def TestInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestInstrInfo;
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let RegistersAreIntervals = 1;
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}
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def sub_lo : SubRegIndex<32>;
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def sub_hi : SubRegIndex<32, 32>;
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let Namespace = "Test" in {
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def R1 : Register<"r1">; // unit 0
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def R2 : Register<"r2">; // unit 1
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def R3 : Register<"r3">; // unit 2
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// First composite: units {0, 1} - contiguous, OK
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def R1_R2 : Register<"r1_r2"> {
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let SubRegs = [R1, R2];
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let SubRegIndices = [sub_lo, sub_hi];
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}
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// Second composite: units {0, 2} - non-contiguous!
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// Algorithm will swap 1 and 2, making R1_R2 not contiguous
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def R1_R3 : Register<"r1_r3"> {
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let SubRegs = [R1, R3];
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let SubRegIndices = [sub_lo, sub_hi];
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}
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}
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def GPR32 : RegisterClass<"Test", [i32], 32, (add R1, R2, R3)>;
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// CHECK: error: cannot enforce regunit intervals, final renumbering did not produce contiguous units for register R1_R2
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