7074471593
We have been tracking the performance of EVL tail folding in the loop vectorizer on RISC-V for a while now, and after much hard work from various contributors we think it should be generally profitable to enable by default now. With tail folding there is a 21% improvement on 525.x264_r on SPEC CPU 2017 on the BPI-F3 (-march=rva22u64_v -O3 -flto), as well as a 30% geomean codesize reduction on SPEC and TSVC, with no significant regressions detected. Now that we are early into the LLVM 22.x development cycle it seems like a good time to enable it to catch any issues. There are still more EVL related items of work being tracked in #123069, which should continue to improve performance.
37 lines
1.6 KiB
LLVM
37 lines
1.6 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfbfmin -prefer-predicate-over-epilogue=scalar-epilogue -debug-only=loop-vectorize,vplan --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s
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; TODO: -prefer-predicate-over-epilogue=scalar-epilogue was added to allow
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; unrolling. Calculate register pressure for all VPlans, not just unrolled ones,
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; and remove.
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define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
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; CHECK-LABEL: add
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; CHECK: LV(REG): Found max usage: 2 item
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; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 3 registers
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; CHECK-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
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; CHECK-NEXT: LV(REG): Found invariant usage: 1 item
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; CHECK-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
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entry:
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%conv = zext i32 %size to i64
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%cmp10.not = icmp eq i32 %size, 0
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br i1 %cmp10.not, label %for.cond.cleanup, label %for.body
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for.cond.cleanup:
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ret void
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for.body:
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%i.011 = phi i64 [ %add4, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds bfloat, ptr %src1, i64 %i.011
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%0 = load bfloat, ptr %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds bfloat, ptr %src2, i64 %i.011
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%1 = load bfloat, ptr %arrayidx2, align 4
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%add = fadd bfloat %0, %1
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%arrayidx3 = getelementptr inbounds bfloat, ptr %result, i64 %i.011
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store bfloat %add, ptr %arrayidx3, align 4
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%add4 = add nuw nsw i64 %i.011, 1
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%exitcond.not = icmp eq i64 %add4, %conv
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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