d611a9ca15
`VPEVLBasedIVPHIRecipe` will lower to VPInstruction scalar phi and generate scalar phi. This recipe will only occupy a scalar register just like other phi recipes. This patch fix the register usage for `VPEVLBasedIVPHIRecipe` from vector to scalar which is close to generated vector IR. https://godbolt.org/z/6Mzd6W6ha shows that no register spills when choosing `<vscale x 16>`. Note that this test is basically copied from AArch64.
34 lines
1.4 KiB
LLVM
34 lines
1.4 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v -vectorizer-maximize-bandwidth -debug-only=loop-vectorize,vplan -disable-output -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-REGS-VP
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define i32 @dotp(ptr %a, ptr %b) {
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; CHECK-REGS-VP: LV(REG): VF = vscale x 16
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; CHECK-REGS-VP-NEXT: LV(REG): Found max usage: 2 item
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; CHECK-REGS-VP-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 6 registers
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; CHECK-REGS-VP-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 24 registers
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; CHECK-REGS-VP-NEXT: LV(REG): Found invariant usage: 1 item
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; CHECK-REGS-VP-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
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; CHECK-REGS-VP: LV: Selecting VF: vscale x 16.
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%accum = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%gep.a = getelementptr i8, ptr %a, i64 %iv
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%load.a = load i8, ptr %gep.a, align 1
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%ext.a = zext i8 %load.a to i32
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%gep.b = getelementptr i8, ptr %b, i64 %iv
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%load.b = load i8, ptr %gep.b, align 1
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%ext.b = zext i8 %load.b to i32
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%mul = mul i32 %ext.b, %ext.a
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%sub = sub i32 0, %mul
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%add = add i32 %accum, %sub
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%iv.next = add i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, 1024
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br i1 %exitcond.not, label %for.exit, label %for.body
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for.exit: ; preds = %for.body
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ret i32 %add
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}
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