d56deea1e4
Update initial construction to connect the Plan's entry to the scalar preheader during initial construction. This moves a small part of the skeleton creation out of ILV and will also enable replacing VPInstruction::ResumePhi with regular VPPhi recipes. Resume phis need 2 incoming values to start with, the second being the bypass value from the scalar ph (and used to replicate the incoming value for other bypass blocks). Adding the extra edge ensures we incoming values for resume phis match the incoming blocks. PR: https://github.com/llvm/llvm-project/pull/140132
99 lines
3.5 KiB
LLVM
99 lines
3.5 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt < %s -passes=loop-vectorize,instcombine -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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; CHECK-LABEL: more_than_one_use
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;
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; PR30627. Check that a compare instruction with more than one use is not
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; recognized as uniform and is vectorized.
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;
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; CHECK-NOT: Found uniform instruction: %cond = icmp slt i64 %i.next, %n
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; CHECK: vector.body
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; CHECK: %[[I:.+]] = add nuw nsw <4 x i64> %vec.ind, splat (i64 1)
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; CHECK: icmp slt <4 x i64> %[[I]], %broadcast.splat
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; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
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;
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define i32 @more_than_one_use(ptr %a, i64 %n) {
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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%r = phi i32 [ %tmp3, %for.body ], [ 0, %entry ]
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%i.next = add nuw nsw i64 %i, 1
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%cond = icmp slt i64 %i.next, %n
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%tmp0 = select i1 %cond, i64 %i.next, i64 0
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%tmp1 = getelementptr inbounds i32, ptr %a, i64 %tmp0
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%tmp2 = load i32, ptr %tmp1, align 8
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%tmp3 = add i32 %r, %tmp2
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br i1 %cond, label %for.body, label %for.end
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for.end:
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%tmp4 = phi i32 [ %tmp3, %for.body ]
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ret i32 %tmp4
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}
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; Check for crash exposed by D76992.
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; CHECK-LABEL: 'test'
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; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
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; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF
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; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
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; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
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; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count
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; CHECK-NEXT: Live-in ir<14> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<entry>:
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; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
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; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]
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; CHECK-NEXT: EMIT vp<[[COND:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
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; CHECK-NEXT: WIDEN ir<%cond0> = icmp ult ir<%iv>, ir<13>
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; CHECK-NEXT: WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>
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; CHECK-NEXT: Successor(s): pred.store
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.store: {
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; CHECK-NEXT: pred.store.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[COND]]>
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; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.if:
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; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
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; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]>
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; CHECK-NEXT: REPLICATE store ir<%s>, ir<%gep>
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; CHECK-NEXT: Successor(s): pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.continue:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): loop.0
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; CHECK-EMPTY:
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; CHECK-NEXT: loop.0:
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
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; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
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; CHECK-NEXT: No successor
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; CHECK-NEXT: }
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define void @test(ptr %ptr) {
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entry:
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br label %loop
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loop: ; preds = %loop, %entry
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%cond0 = icmp ult i64 %iv, 13
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%s = select i1 %cond0, i32 10, i32 20
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%gep = getelementptr inbounds i32, ptr %ptr, i64 %iv
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store i32 %s, ptr %gep
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond = icmp eq i64 %iv.next, 14
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br i1 %exitcond, label %exit, label %loop
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exit:
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ret void
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}
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