08c2f4eb7a
As per the post-commit feedback - that was not the correct precondition to avoid it here. I think we should generally start changing mentality about `freeze`, the fact that we have been conditioned to be afraid of it (or of anything in LLVM in general) is the key problem here.
159 lines
4.5 KiB
LLVM
159 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='default<O1>' -S < %s | FileCheck %s --check-prefixes=CHECK,O1
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; RUN: opt -passes='default<Oz>' -S < %s | FileCheck %s --check-prefixes=CHECK,OZ
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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%struct.a = type { i32 }
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define i32 @PR38781(i32 noundef %a, i32 noundef %b) {
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; CHECK-LABEL: @PR38781(
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[AND1:%.*]] = icmp sgt i32 [[TMP1]], -1
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; CHECK-NEXT: [[AND:%.*]] = zext i1 [[AND1]] to i32
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%cmp = icmp sge i32 %a, 0
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%conv = zext i1 %cmp to i32
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%cmp1 = icmp sge i32 %b, 0
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%conv2 = zext i1 %cmp1 to i32
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%and = and i32 %conv, %conv2
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ret i32 %and
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}
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define i1 @PR54692_a(i8 noundef signext %c) #0 {
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; CHECK-LABEL: @PR54692_a(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[C:%.*]], 32
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; CHECK-NEXT: [[CMP5:%.*]] = icmp eq i8 [[C]], 127
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; CHECK-NEXT: [[OR1:%.*]] = or i1 [[TMP0]], [[CMP5]]
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; CHECK-NEXT: ret i1 [[OR1]]
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;
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entry:
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%conv = sext i8 %c to i32
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%cmp = icmp sge i32 %conv, 0
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br i1 %cmp, label %land.rhs, label %land.end
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land.rhs:
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%conv1 = sext i8 %c to i32
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%cmp2 = icmp sle i32 %conv1, 31
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br label %land.end
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land.end:
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%0 = phi i1 [ false, %entry ], [ %cmp2, %land.rhs ]
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%conv3 = zext i1 %0 to i32
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%conv4 = sext i8 %c to i32
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%cmp5 = icmp eq i32 %conv4, 127
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%conv6 = zext i1 %cmp5 to i32
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%or = or i32 %conv3, %conv6
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%tobool = icmp ne i32 %or, 0
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ret i1 %tobool
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}
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define i1 @PR54692_b(i8 noundef signext %c) {
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; CHECK-LABEL: @PR54692_b(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND1:%.*]] = icmp ult i8 [[C:%.*]], 32
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; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i8 [[C]], 127
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; CHECK-NEXT: [[OR2:%.*]] = or i1 [[AND1]], [[CMP6]]
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; CHECK-NEXT: ret i1 [[OR2]]
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;
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entry:
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%conv = sext i8 %c to i32
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%cmp = icmp sge i32 %conv, 0
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%conv1 = zext i1 %cmp to i32
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%conv2 = sext i8 %c to i32
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%cmp3 = icmp sle i32 %conv2, 31
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%conv4 = zext i1 %cmp3 to i32
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%and = and i32 %conv1, %conv4
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%conv5 = sext i8 %c to i32
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%cmp6 = icmp eq i32 %conv5, 127
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%conv7 = zext i1 %cmp6 to i32
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%or = or i32 %and, %conv7
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%tobool = icmp ne i32 %or, 0
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ret i1 %tobool
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}
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define i1 @PR54692_c(i8 noundef signext %c) {
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; CHECK-LABEL: @PR54692_c(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND1:%.*]] = icmp ult i8 [[C:%.*]], 32
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; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i8 [[C]], 127
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; CHECK-NEXT: [[T0:%.*]] = or i1 [[AND1]], [[CMP6]]
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; CHECK-NEXT: ret i1 [[T0]]
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;
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entry:
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%conv = sext i8 %c to i32
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%cmp = icmp sge i32 %conv, 0
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%conv1 = zext i1 %cmp to i32
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%conv2 = sext i8 %c to i32
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%cmp3 = icmp sle i32 %conv2, 31
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%conv4 = zext i1 %cmp3 to i32
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%and = and i32 %conv1, %conv4
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%tobool = icmp ne i32 %and, 0
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br i1 %tobool, label %lor.end, label %lor.rhs
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lor.rhs:
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%conv5 = sext i8 %c to i32
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%cmp6 = icmp eq i32 %conv5, 127
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br label %lor.end
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lor.end:
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%t0 = phi i1 [ true, %entry ], [ %cmp6, %lor.rhs ]
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ret i1 %t0
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}
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@c = global i32 0, align 4
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declare void @foo(...) #3
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define i32 @PR56119(i32 %e.coerce) {
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; O1-LABEL: @PR56119(
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; O1-NEXT: entry:
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; O1-NEXT: [[CONV2:%.*]] = and i32 [[E_COERCE:%.*]], 255
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; O1-NEXT: [[REM:%.*]] = urem i32 [[CONV2]], 255
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; O1-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 7
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; O1-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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; O1: if.then:
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; O1-NEXT: tail call void (...) @foo()
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; O1-NEXT: br label [[IF_END]]
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; O1: if.end:
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; O1-NEXT: [[TMP0:%.*]] = load i32, ptr @c, align 4
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; O1-NEXT: ret i32 [[TMP0]]
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;
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; OZ-LABEL: @PR56119(
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; OZ-NEXT: entry:
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; OZ-NEXT: [[E_COERCE_FR:%.*]] = freeze i32 [[E_COERCE:%.*]]
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; OZ-NEXT: [[CONV2:%.*]] = and i32 [[E_COERCE_FR]], 255
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; OZ-NEXT: [[CMP1:%.*]] = icmp eq i32 [[CONV2]], 7
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; OZ-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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; OZ: if.then:
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; OZ-NEXT: tail call void (...) @foo()
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; OZ-NEXT: br label [[IF_END]]
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; OZ: if.end:
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; OZ-NEXT: [[TMP0:%.*]] = load i32, ptr @c, align 4
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; OZ-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%e = alloca %struct.a, align 4
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store i32 %e.coerce, ptr %e, align 4
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%0 = load i32, ptr %e, align 4
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%conv = trunc i32 %0 to i8
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%conv1 = trunc i64 -1 to i8
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%conv2 = zext i8 %conv to i32
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%conv3 = zext i8 %conv1 to i32
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%rem = srem i32 %conv2, %conv3
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%conv4 = trunc i32 %rem to i8
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%conv5 = sext i8 %conv4 to i32
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%cmp = icmp eq i32 7, %conv5
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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call void (...) @foo() #5
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br label %if.end
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if.end:
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%1 = load i32, ptr @c, align 4
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ret i32 %1
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}
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