75bb30ddbf
The previous position of llvm.protected.field.ptr lowering for loads and stores was problematic as it not only inhibited optimizations such as DSE (as stores to a llvm.protected.field.ptr were not considered to must-alias stores to the non-protected.field pointer) but also required changes to other optimization passes to avoid transformations that would reduce PFP coverage. Address this by moving the load/store part of the lowering to InstCombine, where it will run earlier than the PFP-breaking and AA-relying transformations. The deactivation symbol, null comparison and EmuPAC parts of the lowering remain in PreISelLowering. Now that the transformation inhibitions are no longer needed, remove them (i.e. partially revert #151649, and revert #182976). This change resulted in a 2.4% reduction in Fleetbench .text size and the following improvements to PFP performance overhead for BM_PROTO_Arena on various microarchitectures: before after Apple M2 Ultra 3.5% 3.3% Google Axion C4A 3.3% 2.9% Google Axion N4A 2.7% 2.2% Reviewers: fmayer, nikic, vitalybuka Reviewed By: fmayer Pull Request: https://github.com/llvm/llvm-project/pull/186548
43 lines
1.7 KiB
LLVM
43 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -O2 -S < %s | FileCheck %s
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; Test that no optimization run at -O2 before InstCombine moves the loads into
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; the exit block, as this causes unnecessary address escapes with pointer field
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; protection.
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define ptr @phi_prot_ptr(i1 %sel, ptr %p1, ptr %p2) {
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; CHECK-LABEL: define ptr @phi_prot_ptr(
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; CHECK-SAME: i1 [[SEL:%.*]], ptr readonly captures(none) [[P1:%.*]], ptr readonly captures(none) [[P2:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: br i1 [[SEL]], label %[[T:.*]], label %[[F:.*]]
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; CHECK: [[T]]:
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[P1]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = tail call i64 @llvm.ptrauth.auth(i64 [[TMP2]], i32 2, i64 1)
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[F]]:
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; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[P2]], align 8
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; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP4]] to i64
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; CHECK-NEXT: [[TMP6:%.*]] = tail call i64 @llvm.ptrauth.auth(i64 [[TMP5]], i32 2, i64 2)
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; CHECK-NEXT: br label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RETVAL_IN:%.*]] = phi i64 [ [[TMP3]], %[[T]] ], [ [[TMP6]], %[[F]] ]
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; CHECK-NEXT: [[RETVAL:%.*]] = inttoptr i64 [[RETVAL_IN]] to ptr
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; CHECK-NEXT: ret ptr [[RETVAL]]
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;
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br i1 %sel, label %t, label %f
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t:
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%protp1 = call ptr @llvm.protected.field.ptr.p0(ptr %p1, i64 1, i1 true)
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%load1 = load ptr, ptr %protp1
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br label %exit
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f:
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%protp2 = call ptr @llvm.protected.field.ptr.p0(ptr %p2, i64 2, i1 true)
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%load2 = load ptr, ptr %protp2
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br label %exit
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exit:
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%retval = phi ptr [ %load1, %t ], [ %load2, %f ]
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ret ptr %retval
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}
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