7d10213317
This reverts commit 43acb61a08fffada31fb2e20e45fcc8492ef76b9.
Recommit the patch after fixing the issue causing the revert in 4e607ec4987.
Extra tests have been added in 5c6cb61ad416a544.
Original commit message:
Extend the NUW/NSW inference logic add in 72121a20cd and cdeaf5f28c3dc
to all overflowing binary operators.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D142721
136 lines
4.8 KiB
LLVM
136 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=ipsccp -S | FileCheck %s
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; x = [10, 21), y = [100, 201)
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; x + y = [110, 221)
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define internal i1 @f.add(i32 %x, i32 %y) {
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; CHECK-LABEL: @f.add(
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; CHECK-NEXT: [[A_1:%.*]] = add nuw nsw i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i32 [[A_1]], 219
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; CHECK-NEXT: [[C_4:%.*]] = icmp slt i32 [[A_1]], 111
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; CHECK-NEXT: [[C_5:%.*]] = icmp eq i32 [[A_1]], 150
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; CHECK-NEXT: [[C_6:%.*]] = icmp slt i32 [[A_1]], 150
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; CHECK-NEXT: [[RES_1:%.*]] = add nuw nsw i1 false, [[C_2]]
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; CHECK-NEXT: [[RES_2:%.*]] = add nuw nsw i1 [[RES_1]], false
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; CHECK-NEXT: [[RES_3:%.*]] = add i1 [[RES_2]], [[C_4]]
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; CHECK-NEXT: [[RES_4:%.*]] = add i1 [[RES_3]], [[C_5]]
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; CHECK-NEXT: [[RES_5:%.*]] = add i1 [[RES_4]], [[C_6]]
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; CHECK-NEXT: ret i1 [[RES_5]]
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;
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%a.1 = add i32 %x, %y
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%c.1 = icmp sgt i32 %a.1, 220
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%c.2 = icmp sgt i32 %a.1, 219
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%c.3 = icmp slt i32 %a.1, 110
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%c.4 = icmp slt i32 %a.1, 111
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%c.5 = icmp eq i32 %a.1, 150
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%c.6 = icmp slt i32 %a.1, 150
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%res.1 = add i1 %c.1, %c.2
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%res.2 = add i1 %res.1, %c.3
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%res.3 = add i1 %res.2, %c.4
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%res.4 = add i1 %res.3, %c.5
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%res.5 = add i1 %res.4, %c.6
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ret i1 %res.5
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}
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define i1 @caller.add() {
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; CHECK-LABEL: @caller.add(
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; CHECK-NEXT: [[CALL_1:%.*]] = tail call i1 @f.add(i32 10, i32 100)
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; CHECK-NEXT: [[CALL_2:%.*]] = tail call i1 @f.add(i32 20, i32 200)
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; CHECK-NEXT: [[RES:%.*]] = and i1 [[CALL_1]], [[CALL_2]]
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%call.1 = tail call i1 @f.add(i32 10, i32 100)
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%call.2 = tail call i1 @f.add(i32 20, i32 200)
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%res = and i1 %call.1, %call.2
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ret i1 %res
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}
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; x = [10, 21), y = [100, 201)
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; x - y = [-190, -79)
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define internal i1 @f.sub(i32 %x, i32 %y) {
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; CHECK-LABEL: @f.sub(
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; CHECK-NEXT: [[A_1:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i32 [[A_1]], -81
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; CHECK-NEXT: [[C_4:%.*]] = icmp slt i32 [[A_1]], -189
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; CHECK-NEXT: [[C_5:%.*]] = icmp eq i32 [[A_1]], -150
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; CHECK-NEXT: [[C_6:%.*]] = icmp slt i32 [[A_1]], -150
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; CHECK-NEXT: [[RES_1:%.*]] = add nuw nsw i1 false, [[C_2]]
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; CHECK-NEXT: [[RES_2:%.*]] = add nuw nsw i1 [[RES_1]], false
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; CHECK-NEXT: [[RES_3:%.*]] = add i1 [[RES_2]], [[C_4]]
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; CHECK-NEXT: [[RES_4:%.*]] = add i1 [[RES_3]], [[C_5]]
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; CHECK-NEXT: [[RES_5:%.*]] = add i1 [[RES_4]], [[C_6]]
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; CHECK-NEXT: ret i1 [[RES_5]]
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;
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%a.1 = sub i32 %x, %y
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%c.1 = icmp sgt i32 %a.1, -80
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%c.2 = icmp sgt i32 %a.1, -81
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%c.3 = icmp slt i32 %a.1, -190
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%c.4 = icmp slt i32 %a.1, -189
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%c.5 = icmp eq i32 %a.1, -150
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%c.6 = icmp slt i32 %a.1, -150
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%res.1 = add i1 %c.1, %c.2
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%res.2 = add i1 %res.1, %c.3
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%res.3 = add i1 %res.2, %c.4
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%res.4 = add i1 %res.3, %c.5
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%res.5 = add i1 %res.4, %c.6
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ret i1 %res.5
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}
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define i1 @caller.sub() {
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; CHECK-LABEL: @caller.sub(
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; CHECK-NEXT: [[CALL_1:%.*]] = tail call i1 @f.sub(i32 10, i32 100)
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; CHECK-NEXT: [[CALL_2:%.*]] = tail call i1 @f.sub(i32 20, i32 200)
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; CHECK-NEXT: [[RES:%.*]] = and i1 [[CALL_1]], [[CALL_2]]
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%call.1 = tail call i1 @f.sub(i32 10, i32 100)
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%call.2 = tail call i1 @f.sub(i32 20, i32 200)
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%res = and i1 %call.1, %call.2
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ret i1 %res
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}
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; x = [10, 21), y = [100, 201)
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; x * y = [1000, 4001)
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define internal i1 @f.mul(i32 %x, i32 %y) {
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; CHECK-LABEL: @f.mul(
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; CHECK-NEXT: [[A_1:%.*]] = mul nuw nsw i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i32 [[A_1]], 3999
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; CHECK-NEXT: [[C_4:%.*]] = icmp slt i32 [[A_1]], 1001
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; CHECK-NEXT: [[C_5:%.*]] = icmp eq i32 [[A_1]], 1500
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; CHECK-NEXT: [[C_6:%.*]] = icmp slt i32 [[A_1]], 1500
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; CHECK-NEXT: [[RES_1:%.*]] = add nuw nsw i1 false, [[C_2]]
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; CHECK-NEXT: [[RES_2:%.*]] = add nuw nsw i1 [[RES_1]], false
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; CHECK-NEXT: [[RES_3:%.*]] = add i1 [[RES_2]], [[C_4]]
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; CHECK-NEXT: [[RES_4:%.*]] = add i1 [[RES_3]], [[C_5]]
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; CHECK-NEXT: [[RES_5:%.*]] = add i1 [[RES_4]], [[C_6]]
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; CHECK-NEXT: ret i1 [[RES_5]]
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;
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%a.1 = mul i32 %x, %y
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%c.1 = icmp sgt i32 %a.1, 4000
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%c.2 = icmp sgt i32 %a.1, 3999
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%c.3 = icmp slt i32 %a.1, 1000
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%c.4 = icmp slt i32 %a.1, 1001
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%c.5 = icmp eq i32 %a.1, 1500
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%c.6 = icmp slt i32 %a.1, 1500
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%res.1 = add i1 %c.1, %c.2
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%res.2 = add i1 %res.1, %c.3
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%res.3 = add i1 %res.2, %c.4
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%res.4 = add i1 %res.3, %c.5
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%res.5 = add i1 %res.4, %c.6
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ret i1 %res.5
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}
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define i1 @caller.mul() {
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; CHECK-LABEL: @caller.mul(
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; CHECK-NEXT: [[CALL_1:%.*]] = tail call i1 @f.mul(i32 10, i32 100)
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; CHECK-NEXT: [[CALL_2:%.*]] = tail call i1 @f.mul(i32 20, i32 200)
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; CHECK-NEXT: [[RES:%.*]] = and i1 [[CALL_1]], [[CALL_2]]
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%call.1 = tail call i1 @f.mul(i32 10, i32 100)
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%call.2 = tail call i1 @f.mul(i32 20, i32 200)
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%res = and i1 %call.1, %call.2
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ret i1 %res
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}
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