bf2f241458
Added support for LShr instructions as base for copyable elements. Also, added simple analysis for best base instruction selection, if multiple candidates are available. Fixed scheduling after cancellation Reviewers: hiraditya, RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/153393
55 lines
2.4 KiB
LLVM
55 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S --passes=slp-vectorizer -slp-threshold=-100 -mtriple=arm64-apple-macosx13.0.0 < %s | FileCheck %s
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define i32 @test(ptr %c) {
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; CHECK-LABEL: define i32 @test(
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; CHECK-SAME: ptr [[C:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[BITLEN:%.*]] = getelementptr i8, ptr [[C]], i64 136
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; CHECK-NEXT: [[INCDEC_PTR_3_1:%.*]] = getelementptr i8, ptr [[C]], i64 115
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; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[BITLEN]], align 8
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 0, i32 0, i32 0>
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; CHECK-NEXT: [[TMP5:%.*]] = lshr <8 x i64> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i64> [[TMP5]] to <8 x i8>
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; CHECK-NEXT: store <8 x i8> [[TMP6]], ptr [[INCDEC_PTR_3_1]], align 1
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%bitlen = getelementptr i8, ptr %c, i64 136
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%0 = load i64, ptr %bitlen, align 8
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%incdec.ptr.4 = getelementptr i8, ptr %c, i64 122
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%shr45.4 = lshr i64 %0, 0
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%conv43.5 = trunc i64 %shr45.4 to i8
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%incdec.ptr.5 = getelementptr i8, ptr %c, i64 121
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store i8 %conv43.5, ptr %incdec.ptr.4, align 1
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%shr45.5 = lshr i64 %0, 0
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%conv43.6 = trunc i64 %shr45.5 to i8
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%incdec.ptr.6 = getelementptr i8, ptr %c, i64 120
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store i8 %conv43.6, ptr %incdec.ptr.5, align 1
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%conv43.7 = trunc i64 %0 to i8
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%incdec.ptr.7 = getelementptr i8, ptr %c, i64 119
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store i8 %conv43.7, ptr %incdec.ptr.6, align 1
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%arrayidx38.1 = getelementptr i8, ptr %c, i64 144
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%1 = load i64, ptr %arrayidx38.1, align 8
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%conv43.145 = trunc i64 %1 to i8
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%incdec.ptr.146 = getelementptr i8, ptr %c, i64 118
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store i8 %conv43.145, ptr %incdec.ptr.7, align 1
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%shr45.147 = lshr i64 %1, 0
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%conv43.1.1 = trunc i64 %shr45.147 to i8
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%incdec.ptr.1.1 = getelementptr i8, ptr %c, i64 117
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store i8 %conv43.1.1, ptr %incdec.ptr.146, align 1
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%shr45.1.1 = lshr i64 %1, 0
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%conv43.2.1 = trunc i64 %shr45.1.1 to i8
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%incdec.ptr.2.1 = getelementptr i8, ptr %c, i64 116
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store i8 %conv43.2.1, ptr %incdec.ptr.1.1, align 1
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%shr45.2.1 = lshr i64 %1, 0
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%conv43.3.1 = trunc i64 %shr45.2.1 to i8
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%incdec.ptr.3.1 = getelementptr i8, ptr %c, i64 115
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store i8 %conv43.3.1, ptr %incdec.ptr.2.1, align 1
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%shr45.3.1 = lshr i64 %1, 0
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%conv43.4.1 = trunc i64 %shr45.3.1 to i8
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store i8 %conv43.4.1, ptr %incdec.ptr.3.1, align 1
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ret i32 0
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}
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